TPS54227

(HSOP8)

PowerPAD

TM

1

2

3

4

8

7

6

5

SW

GND

VBST

VIN

EN

VFB

VREG5

SS

EN

VFB

VREG5

SS

GND

VIN

VIN

VBST

SW

SW

Exposed

Thermal

Die PAD

on

Underside

PGND

1

2

3

4

5

10

9

8

7

6

TPS54227

SLVSAU2B – MAY 2011 – REVISED JUNE 2013

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ON-TIME TIMER CONTROL

On time

150

ns

Minimum off time

260

310

ns

SOFT START

SS charge current

1.4

2.0

2.6

μA

SS discharge current

0.1

0.2

mA

UVLO

3.45

3.75

4.05

UVLO

UVLO threshold

V

0.13

0.32

0.48

DEVICE INFORMATION

DDA PACKAGE

DRC PACKAGE

(TOP VIEW)

(TOP VIEW)

PIN FUNCTIONS

PIN

DESCRIPTION

NAME

DDA

DRC

EN

1

1

Enable input control. EN is active high and must be pulled up to enable the device.

VFB

2

2

Converter feedback input. Connect to output voltage with feedback resistor divider.

5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is

VREG5

3

3

not active when EN is low.

SS

4

4

Soft-start control. An external capacitor should be connected to GND.

Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns

GND

5

5

to GND at a single point.

SW

6

6, 7

Switch node connection between high-side NFET and low-side NFET.

Supply input for the high-side FET gate drive circuit. Connect 0.1 µF capacitor between VBST

VBST

7

8

and SW pins. An internal diode is connected between VREG5 and VBST.

VIN

8

9, 10

Input voltage supply pin.

Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be

Back side

connected to GND.

Exposed

Thermal Pad

Thermal pad of the package. PGND power ground return of internal low-side FET. Must be

Back side

soldered to achieve appropriate dissipation.

4

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Product Folder Links: TPS54227