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CB3LV Datasheet(PDF) 3 Page - CTS Corporation |
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CB3LV Datasheet(HTML) 3 Page - CTS Corporation |
3 / 4 page Document No. 008-0256-0 Page 3 - 4 Rev. F ٠ ٠ ٠ CTS Electronic Components, Inc. ٠ 171 Covington Drive ٠ Bloomingdale, IL 60108 ٠ ٠ ٠ Model CB3 & CB3LV 7.0x5.0mm Low Cost HCMOS/TTL Clock Oscillator MECHANICAL SPECIFICATIONS CMOS/TTL OUTPUT WAVEFORM TEST CIRCUIT, CMOS LOAD ENABLE TRUTH TABLE PIN 1 PIN 3 Logic ‘1’ Output Open Output Logic ‘0’ High Imp. D.U.T. PIN ASSIGNMENTS PIN SYMBOL DESCRIPTION 1 EOH Enable Input 2 GND Circuit & Package Ground 3 Output RF Output 4 VCC Supply Voltage MARKING INFORMATION 1. ** – Manufacturing Site Code. [Note a dash may follow the site code and is acceptable.] 2. XXXMXXXXXX – Frequency is marked with only leading significant digits before the ‘M’ and 4 - 6 digits after the ‘M’ (including zeros). Ex. XMXXXXXX (3M579545) XXMXXXXX (14M31818) XXXMXXXX (125M0000) 3. YYWW – Date code, YY – year, WW – week. 4. ST – Frequency stability/temperature code. (Refer to Ordering Information.) 5. V – Voltage code. 3 = 3.3V, 5 = 5.0V. NOTES 1. Termination pads (e4). Barrier-plating is nickel (Ni) with gold (Au) flash plate. 2. Reflow conditions per JEDEC J-STD-020. PERIOD (T) 90%, 80%, 2.4V 50%, 1.5V 10%, 20%, 0.5V DUTY CYCLE = t/T x 100 (%) V V OH OL Tr Tf UPTIME (t) POWER SUPPLY + - +- - + VM mA .01uF D.U.T. 43 12 C L Including probe capacitance. Enable Input SUGGESTED SOLDER PAD GEOMETRY .200 [5.08] .165 [4.20] .071 [1.80] Key: [mm] Inch .079 [2.00] 12 3 4 C BYPASS CBYPASS should be ≥ 0.01 uF. PACKAGE DRAWING (1.7) MAX (7.0 ±0.2) (5.08) 0.200 0.055 0.276 ±0.008 0.067 (5.0 ±0.2) 0.197 ±0.008 (1.4) 0.146 (3.7) Key: (mm) Inch 2 34 PIN 1 IDENTIFIER 0.047 (1.2) 1 CTS ** CB3 XXXMXXXXXX ● YYWW STV |
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