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MCF5274CVM166 Datasheet(PDF) 34 Page - Freescale Semiconductor, Inc |
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MCF5274CVM166 Datasheet(HTML) 34 Page - Freescale Semiconductor, Inc |
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34 / 44 page  MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4 Electrical Characteristics Freescale Semiconductor 34 8.11 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at 5.0 V or 3.3 V. 8.11.1 MII Receive Signal Timing (FECn_RXD[3:0], FECn_RXDV, FECn_RXER, and FECn_RXCLK) The receiver functions correctly up to a FECn_RXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the FECn_RXCLK frequency. Table 18 lists MII receive channel timings. Figure 16 shows MII receive signal timings listed in Table 18. Figure 16. MII Receive Signal Timing Diagram 8.11.2 MII Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK) Table 19 lists MII transmit channel timings. The transmitter functions correctly up to a FECn_TXCLK maximum frequency of 25 MHz +1%. The processor clock frequency must exceed twice the FECn_TXCLK frequency. Table 18. MII Receive Signal Timing Num Characteristic Min Max Unit M1 FECn_RXD[3:0], FECn_RXDV, FECn_RXER to FECn_RXCLK setup 5— ns M2 FECn_RXCLK to FECn_RXD[3:0], FECn_RXDV, FECn_RXER hold 5— ns M3 FECn_RXCLK pulse width high 35% 65% FECn_RXCLK period M4 FECn_RXCLK pulse width low 35% 65% FECn_RXCLK period M1 M2 FECn_RXCLK (input) FECn_RXD[3:0] (inputs) FECn_RXDV FECn_RXER M3 M4 |
Similar Part No. - MCF5274CVM166 |
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Similar Description - MCF5274CVM166 |
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