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DDC114IRTCR Datasheet(PDF) 11 Page - Texas Instruments |
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DDC114IRTCR Datasheet(HTML) 11 Page - Texas Instruments |
11 / 35 page DDC114 SBAS255C − JUNE 2004 − REVISED APRIL 2009 www.ti.com 11 At the completion of an A/D conversion, the charge on the integration capacitor (CF) is reset with SREF1 and SRESET (see Figure 4 and Figure 5a). In this manner, the selected capacitor is charged to the reference voltage, VREF. Once the integration capacitor is charged, SREF1 and SRESET are switched so that VREF is no longer connected to the amplifier circuit while it waits to begin integrating (see Figure 5b). With the rising edge of CONV, SINTA closes, which begins the integration of side A. This process puts the integrator stage into its integrate mode (see Figure 5c). Charge from the input signal is collected on the integration capacitor, causing the voltage output of the amplifier to decrease. The falling edge of CONV stops the integration by switching the input signal from side A to side B (SINTA and SINTB). Prior to the falling edge of CONV, the signal on side B was converted by the A/D converter and reset during the time that side A was integrating. With the falling edge of CONV, side B starts integrating the input signal. Now the output voltage of the side A operational amplifier is presented to the input of the ∆Σ A/D converter (see Figure 5d). Integration Capacitors There are eight different capacitors available on-chip for both sides of every channel in the DDC114. These internal capacitors are trimmed in production to achieve the specified performance for range error of the DDC114. The range control pins (RANGE0 −RANGE2) change the capacitor value for all four integrators. Consequently, all inputs and both sides of each input will always have the same full-scale range. Table 1 shows the capacitor value selected for each range selection. Table 1. Range Selection of the DDC114 RANGE2 RANGE1 RANGE0 CF (pF, typ) INPUT RANGE (pC, typ) 0 0 0 3 −0.048 to 12 0 0 1 12.5 –0.2 to 50 0 1 0 25 –0.4 to 100 0 1 1 37.5 –0.6 to 150 1 0 0 50 –0.8 to 200 1 0 1 62.5 –0.1 to 250 1 1 0 75 –1.2 to 300 1 1 1 87.5 –1.4 to 350 Voltage Reference The external voltage reference is used to reset the integration capacitors before an integration cycle begins. It is also used by the ∆Σ converter while the converter is measuring the voltage stored on the integrators after an integration cycle ends. During this sampling, the external reference must supply the charge needed by the ∆Σ converter. For an integration time of 400 µs, this charge translates to an average VREF current of approximately 75 µA. The amount of charge needed by the ∆Σ converter is independent of the integration time; therefore, increasing the integration time lowers the average current. For example, an integration time of 800 µs lowers the average VREF current to 37.5 µA. It is critical that VREF be stable during the different modes of operation (see Figure 5). The ∆Σ converter measures the voltage on the integrator with respect to VREF. Since the integrator capacitors are initially reset to VREF, any drop in VREF from the time the capacitors are reset to the time when the converter measures the integrator output will introduce an offset. It is also important that VREF be stable over longer periods of time because changes in VREF correspond directly to changes in the full-scale range. Finally, VREF should introduce as little additional noise as possible. For these reasons, it is strongly recommended that the external reference source be buffered with an operational amplifier, as shown in Figure 6. In this circuit, the voltage reference is generated by a 4.096V reference. A low-pass filter to reduce noise connects the reference to an operational amplifier configured as a buffer. This amplifier should have low noise and input/output common-mode ranges that support VREF. Following the buffer are capacitors placed close to the DDC114 VREF pin. Even though the circuit in Figure 6 might appear to be unstable because of the large output capacitors, it works well for most operational amplifiers. It is NOT recommended that series resistance be placed in the output lead to improve stability since this can cause a drop in VREF, producing large offsets. 0.10 µF +5V 10k Ω 10 µF 4 3 2 3 1 2 7 6 + 0.10 µF 0.1 µF 10 µF + OPA350 0.47 µF +5V To VREF Pin10of the DDC114 REF3140 Figure 6. Recommended External Voltage Reference Circuit for Best Low-Noise Operation with the DDC114 |
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