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AM29LV640DU120RFIN Datasheet(PDF) 27 Page - Advanced Micro Devices |
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AM29LV640DU120RFIN Datasheet(HTML) 27 Page - Advanced Micro Devices |
27 / 57 page 26 Am29LV640D/Am29LV641D September 20, 2002 hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- d ard program comman d sequen ce . The u nlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 10 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. The device offers accelerated program operations through the ACC pin. When the system asserts V HH on the ACC pin, the device automatically enters the Un- lock Bypass mode. The system may then write the two-cycle Unlock Bypass program command se- quence. The device uses the higher voltage on the ACC pin to accelerate the operation. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may re- sult. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 15 for timing diagrams. Figure 3. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any con- trols or timings during these operations. Table 10 shows the address and data requirements for the chip erase command sequence. START Write Program Command Sequence Data Poll from System Verify Data? No Yes Last Address? No Yes Programming Completed Increment Address Embedded Program algorithm in progress Note: See Table 10 for program command sequence. |
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