LM2641

SNVS040B – JANUARY 2000 – REVISED APRIL 2013

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Connection Diagram

Figure 1. 28-Lead TSSOP (PW)

Top View

See Package Number PW0028A

Pin #

Name

Function

1

CSH2

The sense point for the positive side of the voltage across the current sense resistor (R13) placed in

series with output #2.

2

FB2

The regulated output voltage appearing at output #2 is sensed using this pin by connecting it to the

center of the output resistive divider (R15 and R16).

3

COMP2

An R-C network made up of R11, C10, and C12 is connected to this pin which provides loop

compensation for regulated output #2.

4

SS2

This provides programmable soft-start for the #2 output along with capacitor C15.

5

ON/OFF2

This pin turns off only output #2.

6

SD

The part can be put into “sleep” mode using this pin, where both outputs are off and the internal chip

functions are shut down.

7

SYNC

The internal oscillator may be synchronized to an external clock via this pin.

8

GND

Connect this pin to circuit Signal Ground.

9

REF

Internal 2.5V reference voltage. This voltage is turned off by the SD pin, but remains on if either or both

ON/OFF pins are pulled low, which turns off the regulated output(s).

10

2NDFB/FPWM

A 12V supply can be generated using an auxiliary winding on the 5V output inductor. Feedback to

control this 12V output is brought in through this pin. If the 12V supply is not required, this pin can also

force the chip to operate at fixed frequency at light loads by pulling the pin low (this is the “forced-PWM”

mode of operation). This will prevent the converter from operating in pulse-skipping mode.

11

ON/OFF1

This pin turns off only output #1.

12

SS1

This provides programmable soft-start for the #1 output along with capacitor C3.

13

COMP1

An R-C network made up of R6, C5, and C7 is connected to this pin which provides loop compensation

for regulated output #1.

14

FB1

The regulated output voltage appearing at output #1 is sensed using this pin by connecting it to the

center of the output resistive divider (R1 and R2).

15

CSH1

The sense point for the positive side of the voltage across the current sense resistor (R4) placed in

series with output #1.

16

HDRV1

The drive for the gate of the high-side switching FET used for output #1.

17

SW1

This is the switching output drive point of the two power FETs which produce output #1.

18

CBOOT1

The bootstrap capacitor (C8) for output #1 is returned to this point.

19

LDRV1

The drive for the gate of the low-side switching FET (synchronous rectifier) used for output #1.

20

PGND

Connect this pin to circuit Power Ground.

(1)

(Refer to Typical Application Circuits)

2

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