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PCF8583P Datasheet(PDF) 22 Page - NXP Semiconductors

Part No. PCF8583P
Description  Clock and calendar with 240 x 8-bit RAM
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCF8583P Datasheet(HTML) 22 Page - NXP Semiconductors

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PCF8583
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 6 October 2010
22 of 37
NXP Semiconductors
PCF8583
Clock and calendar with 240 x 8-bit RAM
10.2 Dynamic characteristics
[1]
Event counter mode only.
[2]
All timing values are valid within the operating supply voltage, ambient temperature range, reference to VIL and VIH and with an input
voltage swing of VSS to VDD.
Table 8.
Dynamic characteristics
VDD = 2.5 V to 6.0 V; VSS = 0 V; Tamb = 40 °C to +85 °C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Oscillator
COSCO
capacitance on pin OSCO
-
40
-
pF
Δf
osc/fosc
relative oscillator frequency
variation
for
ΔV
DD = 100 mV; Tamb =25 °C;
VDD = 1.5 V
-0.2
-ppm
fclk(ext)
external clock frequency
on pin OSCI
[1]
--1
MHz
Quartz crystal parameters (f = 32.768 kHz)
RS
series resistance
-
-
40
k
Ω
CL
parallel load capacitance
-
10
-
pF
Ctrim
trimmer capacitance
5
-
25
pF
I2C-bus timing (see Figure 21)[2]
fSCL
SCL clock frequency
-
-
100
kHz
tSP
pulse width of spikes that
must be suppressed by the
input filter
--100
ns
tBUF
bus free time between a
STOP and START condition
4.7
-
-
μs
tSU;STA
set-up time for a repeated
START condition
4.7
-
-
μs
tHD;STA
hold time (repeated) START
condition
4.0
-
-
μs
tLOW
LOW period of the SCL clock
4.7
-
-
μs
tHIGH
HIGH period of the SCL clock
4.0
-
-
μs
tr
rise time of both SDA and
SCL signals
--1.0
μs
tf
fall time of both SDA and SCL
signals
--0.3
μs
tSU;DAT
data set-up time
250
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
tVD;DAT
data valid time
-
-
3.4
μs
tSU;STO
set-up time for STOP
condition
4.0
-
-
μs


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