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PCF8583P Datasheet(PDF) 15 Page - NXP Semiconductors

Part No. PCF8583P
Description  Clock and calendar with 240 x 8-bit RAM
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCF8583P Datasheet(HTML) 15 Page - NXP Semiconductors

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PCF8583
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 06 — 6 October 2010
15 of 37
NXP Semiconductors
PCF8583
Clock and calendar with 240 x 8-bit RAM
8.
Characteristics of the I2C-bus
8.1 Characteristics
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when
the bus is not busy.
8.1.1 Bit transfer
One data bit is transferred during each clock pulse (see Figure 14). The data on the SDA
line must remain stable during the HIGH period of the clock pulse as changes in the data
line at this time are interpreted as a control signal.
8.1.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 15).
8.1.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver (see Figure 16). The device that controls the message is the master; and the
devices which are controlled by the master are the slaves.
Fig 14. Bit transfer
mbc621
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig 15. Definition of start and stop conditions
mbc622
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition


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