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PCF8583P Datasheet(PDF) 13 Page - NXP Semiconductors |
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PCF8583P Datasheet(HTML) 13 Page - NXP Semiconductors |
13 / 37 page ![]() PCF8583 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 06 — 6 October 2010 13 of 37 NXP Semiconductors PCF8583 Clock and calendar with 240 x 8-bit RAM this mode, the timer (location 07h) increments once for every one, one hundred, ten thousand, or 1 million events, depending on the value programmed in bits 0, 1 and 2 of the alarm control register. In all other events, the timer functions are as in the clock mode. 7.9 Interrupt output The conditions for activating the output INT (active LOW) are determined by appropriate programming of the alarm control register. These conditions are clock alarm, timer alarm, timer overflow, and event counter alarm. An interrupt occurs when the alarm flag or the timer flag is set, and the corresponding interrupt is enabled. In all events, the interrupt is cleared only by software resetting of the flag which initiated the interrupt. In the clock mode, if the alarm enable is not activated (alarm enable bit of the control and status register is logic 0), the interrupt output toggles at 1 Hz with a 50 % duty cycle (may be used for calibration). This is the default power-on state of the device. The OFF voltage of the interrupt output may exceed the supply voltage, up to a maximum of 6.0 V. A logic diagram of the interrupt output is shown in Figure 12. 7.10 Oscillator and divider A 32.768 kHz quartz crystal has to be connected to OSCI and OSCO. A trimmer capacitor between OSCI and VDD is used for tuning the oscillator (see Section 11.1). A 100 Hz clock signal is derived from the quartz oscillator for the clock counters. Fig 13. Alarm control register, event counter mode memory location 08h reset state: 0000 0000 timer function: clock alarm function: timer alarm enable: alarm interrupt enable: 7 654 321 0 MSB LSB 013aaa376 000 001 010 011 100 101 110 111 no timer units 100 10 000 1 000 000 not allowed not allowed test mode, all counters in parallel timer interrupt enable: 0 1 timer flag, no interrupt timer flag, interrupt 00 01 10 11 no event alarm event alarm not allowed not allowed 0 1 no timer alarm timer alarm 0 1 alarm flag, no interrupt alarm flag, interrupt |
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