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IDT5T9306NLGI Datasheet(PDF) 3 Page - List of Unclassifed Manufacturers |
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IDT5T9306NLGI Datasheet(HTML) 3 Page - List of Unclassifed Manufacturers |
3 / 16 page IDT5T9306 REVISION B JANUARY 31, 2011 3 ©2011 Integrated Device Technology, Inc. IDT5T9306 Data Sheet 2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II Symbol Description Max Unit VDD Power Supply Voltage –0.5 to +3.6 V VI Input Voltage –0.5 to +3.6 V VO Output Voltage(2) –0.5 to VDD +0.5 V TSTG Storage Temperature –65 to +150 °C TJ Junction Temperature 150 °C ABSOLUTE MAXIMUM RATINGS(1) NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Not to exceed 3.6V. Symbol Parameter Min Typ. Max. Unit CIN Input Capacitance —— 3pF CAPACITANCE(1) (TA = +25°C, F = 1.0MHz) NOTE: 1. This parameter is measured at characterization but not tested Symbol Description Min. Typ. Max. Unit TA AmbientOperatingTemperature –40 +25 +85 °C VDD InternalPowerSupplyVoltage 2.3 2.5 2.7 V RECOMMENDED OPERATING RANGE PIN DESCRIPTION Symbol I/O Type Description A[1:2] I Adjustable(1,4) Clock input. A[1:2] is the "true" side of the differential clock input. A[1:2] I Adjustable(1,4) Complementary clock inputs. A[1:2] is the complementary side of A[1:2]. For LVTTL single-ended operation, A[1:2] should be set to the desiredtogglevoltageforA[1:2]: 3.3V LVTTL VREF = 1650mV 2.5V LVTTL VREF = 1250mV G I LVTTL Gate control for differential outputs Q1 and Q1 through Q6 and Q6. When Gis LOW, the differential outputs are active. When Gis HIGH, the differential outputs are asynchronously driven to the level designated by GL(2). GL I LVTTL Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true" outputsdisableLOWand"complementary"outputsdisableHIGH. Qn O LVDS Clockoutputs Qn O LVDS Complementaryclockoutputs SEL I LVTTL Reference clock select. When LOW, selects A2 and A2. When HIGH, selects A1 and A1. PD I LVTTL Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both "true" and "complementary" outputs will pull to VDD. Set HIGH for normal operation.(3) VDD PWR Power supply for the device core and inputs GND PWR Power supply return for all power N C No connect; recommended to connect to GND NOTES: 1. Inputs are capable of translating the following interface standards: Single-ended 3.3V and 2.5V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL (2.5V) and LVPECL (3.3V) levels Differential LVDS levels Differential CML levels 2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power- up after asserting PD. 4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal. |
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