IDT5T9306 REVISION B JANUARY 31, 2011

3

©2011 Integrated Device Technology, Inc.

IDT5T9306 Data Sheet

2.5V LVDS 1:6 CLOCK BUFFER TERABUFFER™ II

Symbol

Description

Max

Unit

Power Supply Voltage

–0.5 to +3.6

V

Input Voltage

–0.5 to +3.6

V

V

Storage Temperature

–65 to +150

°C

Junction Temperature

150

°C

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Not to exceed 3.6V.

Symbol

Parameter

Min

Typ.

Max.

Unit

Input Capacitance

——

3pF

NOTE:

1. This parameter is measured at characterization but not tested

Symbol

Description

Min.

Typ.

Max.

Unit

AmbientOperatingTemperature

–40

+25

+85

°C

InternalPowerSupplyVoltage

2.3

2.5

2.7

V

RECOMMENDED OPERATING RANGE

PIN DESCRIPTION

Symbol

I/O

Type

Description

I

I

G

I

LVTTL

GL

I

LVTTL

Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"

outputsdisableLOWand"complementary"outputsdisableHIGH.

Qn

O

LVDS

Clockoutputs

Qn

O

LVDS

Complementaryclockoutputs

SEL

I

LVTTL

PD

I

LVTTL

Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both

PWR

Power supply for the device core and inputs

GND

PWR

Power supply return for all power

N C

No connect; recommended to connect to GND

NOTES:

1. Inputs are capable of translating the following interface standards:

Single-ended 3.3V and 2.5V LVTTL levels

Differential HSTL and eHSTL levels

Differential LVEPECL (2.5V) and LVPECL (3.3V) levels

Differential LVDS levels

Differential CML levels

2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt

pulses or be able to tolerate them in down stream circuitry.

3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-

up after asserting PD.

4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.