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5962R9563001QXC Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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5962R9563001QXC Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
4 / 27 page STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95630 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL N SHEET 4 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Positive supply voltage (V+): Device types 01, 02, and 04 .................................................................................. +15 V Device types 03 and 05 ......................................................................................... +12 V ±10% Negative supply voltage (V-): Device types 01, 02, and 04 .................................................................................. -15 V Device types 03 and 05 ......................................................................................... -12 V ±10% VREF .......................................................................................................................... 5 V dc VAH ............................................................................................................................ 4.0 V dc VAL ............................................................................................................................ 0.8 V dc VEN ............................................................................................................................ 0.8 V dc Ambient operating temperature range (TA) ............................................................... -55°C to +125°C 1.5 Radiation features. Maximum total dose available: high dose rate tests - dose rate = 50 – 300 rad(Si)/s Device classes Q and V: Device type 01 ................................................................................................... 200 krads(Si) Device types 02, 03, 04 and 05 .......................................................................... 300 krads(Si) Device class T: Device type 02 ................................................................................................... 100 krads(Si) ELDRS test (Low dose rate < 10 mrad(Si)/s: Device class V: Device types 02 and 03 ......................................................................................... Not production tested 3/ Device types 04 and 05 .......................................................................................... 50 krads(Si) 3/ 4/ Single event phenomena (SEP) : No SEL occurs at effective linear energy threshold (LET): Device type 01 ................................................................................................... ≤110 MeV/cm 2 /mg 5/ Device types 02, 03, 04, and 05 ......................................................................... Latch up free 5/ Dose rate induced latch up: Device type 01 ....................................................................................................... None 6/ Device types 02, 03, 04, and 05 ............................................................................ Not tested Dose rate upset: Device type 01 ....................................................................................................... ≥1 x 10 8 rads(Si)/s Device types 02, 03, 04, and 05 ............................................................................ Not tested For device types 02, 03, 04 and 05, the manufacturer supplying RHA parts on this drawing has performed characterization testing to a level of 150 krad(Si) that demonstrates the parts do not exhibit enhanced low dose rate sensitivity (ELDRS) according to MIL-STD-883 method 1019 paragraph 3.13.1.1. Therefore, this part may be considered ELDRS free. Testing beyond 150 krads(Si) was not performed. ______ 3/ For device types 02, 03, 04 and 05, the manufacturer supplying RHA parts on this drawing has performed characterization testing to a level of 150 krad(Si) at low and high dose rate in accordance with MIL-STD-883 method 1019 paragraph 3.13.1.1. Therefore, this part may be considered ELDRS free. Testing beyond 150 krads(Si) was not performed. 4/ Devices 04 and 05 are production lot acceptance tested on a wafer by wafer basis to 50 krads(Si) at low dose rate (< 10 mrad(Si)/s). 5/ Device type 01 uses dielectrically isolated (DI) / CMOS technology and latch-up is physically not possible. Device types 02, 03, 04, and 05 use dielectrically isolated (DI) technology and latch-up is physically not possible. 6/ Guaranteed by process design, but not tested, unless specified in table IA herein. |
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