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74HCT4067D Datasheet(PDF) 18 Page - NXP Semiconductors |
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74HCT4067D Datasheet(HTML) 18 Page - NXP Semiconductors |
18 / 30 page ![]() 74HC_HCT4067 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 5 — 13 December 2011 18 of 30 NXP Semiconductors 74HC4067; 74HCT4067 16-channel analog multiplexer/demultiplexer [1] For 74HCT4067: maximum input voltage VI = 3.0 V. Test data is given in Table 12. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistor. S1 = Test selection switch. Fig 14. Load circuitry for measuring switching times VM VM tW tW 10 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % tf tr tr tf 001aag732 VCC VCC open GND VI Vos DUT CL RT RL S1 PULSE GENERATOR Vis Table 12. Test data Test Input Output S1 position Control E Address Sn Switch Yn (Z) tr, tf Switch Z (Yn) VI[1] VI[1] Vis CL RL tPHL, tPLH GND GND or VCC GND to VCC 6ns 50pF - open tPHZ, tPZH GND to VCC GND to VCC VCC 6ns 50pF, 15pF 1k GND tPLZ, tPZL GND to VCC GND to VCC GND 6 ns 50 pF, 15 pF 1 k VCC |
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