TMS27C512 65536 BY 8BIT UV ERASABLE

TMS27PC512 65536 BY 8BIT

PROGRAMMABLE READONLY MEMORIES

SMLS512G − NOVEMBER 1985 − REVISED SEPTEMBER 1997

9

POST OFFICE BOX 1443

timing requirements for programming

MIN

NOM

MAX

UNIT

tw(IPGM)

Pulse duration, initial program

95

100

105

µs

tsu(A)

Setup time, address

2

µs

tsu(D)

Setup time, data

2

µs

tsu(VPP

Setup time, G /VPP

2

µs

tsu(VCC)

Setup time, VCC

2

µs

th(A)

Hold time, address

0

µs

th(D)

Hold time, data

2

µs

th(VPP)

Hold time, G /VPP

2

µs

trec(PG)

Recovery time, G /VPP

2

µs

tEHD

Data valid from E low

1

µs

tr(PG)G

Rise time, G /VPP

50

ns

PARAMETER MEASUREMENT INFORMATION

2.08 V

RL = 800 Ω

Output

Under Test

CL = 100 pF

(see Note A)

2.4 V

0.4 V

2 V

0.8 V

2 V

0.8 V

NOTES: A. CL includes probe and fixture capacitance.

B. The ac testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing

measurements are made at 2 V for logic high and 0.8 V for logic low for both inputs

and outputs.

Figure 2. AC Testing Output Load Circuit