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TMS27C240-10JL Datasheet(PDF) 9 Page - Texas Instruments

Part No. TMS27C240-10JL
Description  TMS27C240 262144 BY 16-BIT UV ERASABLE TM27PC240 262144 BY 16-BIT
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TMS27C240-10JL Datasheet(HTML) 9 Page - Texas Instruments

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TMS27C240 262144 BY 16BIT UV ERASABLE
TMS27PC240 262144 BY 16BIT
PROGRAMMABLE READONLY MEMORIES
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VOH High-level dc output voltage
IOH = − 400 µA
2.4
V
VOH High-level dc output voltage
IOH = − 20 µA
VCC − 0.1
V
VOL
Low-level dc output voltage
IOL = 2.1 mA
0.4
V
VOL
Low-level dc output voltage
IOL = 20 µA
0.1
V
II
Input current (leakage)
VI = 0 V to 5.5 V
±1
µA
IO
Output current (leakage)
VO = 0 V to VCC
±1
µA
IPP1 VPP supply current
VPP = VCC = 5.5 V
10
µA
IPP2 VPP supply current (during program pulse)
VPP = 13 V
50
mA
ICC1 VCC supply current (standby)
VCC = 5.5 V,
E = VIH
1
mA
ICC1 VCC supply current (standby)
VCC = 5.5 V,
E = VCC
100
µA
ICC2 VCC supply current (active)
VCC = 5.5 V,
E = VIL,
tcycle = minimum cycle time,
outputs open
50
mA
capacitance
over
recommended
ranges
of
supply
voltage
and
operating
free-air
temperature, f = 1 MHz
PARAMETER
TEST CONDITIONS
MIN
TYP‡
MAX
UNIT
Ci
Input capacitance
VI = 0 V
4
8
pF
Co
Output capacitance
VO = 0 V
8
12
pF
† Capacitance measurements are made on a sample basis only.
‡ Typical values are at TA = 25°C and nominal voltages.
switching characteristics over recommended ranges of operating conditions (see Notes 3
and 4)
PARAMETER
TEST CONDITIONS
’27C240 - 10
’27 PC240 - 10
’27C240 - 12
’27 PC240 - 12
’27C240 - 15
’27 PC240 - 15
UNIT
PARAMETER
TEST CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ta(A)
Access time from address
100
120
150
ns
ta(E)
Access time from chip enable
CL = 100 pF,
100
120
150
ns
ten(G)
Output enable time from G
CL = 100 pF,
1 Series 74
TTL load,
50
50
50
ns
tdis
Output disable time from G or E, whichever
occurs first†
1 Series 74
TTL load,
Input tr ≤ 20 ns,
Input tf ≤ 20 ns
0
50
0
50
0
50
ns
tv(A)
Output data valid time after change of
address, E, or G, whichever occurs first§
Input tf ≤ 20 ns
0
0
0
ns
§ Value calculated from 0.5 V delta to measured level.
NOTES:
3. For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low (see Figure 2).
4. Common test conditions apply for tdis except during programming.


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