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TMS27C240-10JL Datasheet(PDF) 4 Page - Texas Instruments

Part No. TMS27C240-10JL
Description  TMS27C240 262144 BY 16-BIT UV ERASABLE TM27PC240 262144 BY 16-BIT
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TMS27C240-10JL Datasheet(HTML) 4 Page - Texas Instruments

 
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TMS27C240 262144 BY 16BIT UV ERASABLE
TMS27PC240 262144 BY 16BIT
PROGRAMMABLE READONLY MEMORIES
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
latchup immunity
Latchup immunity on the TMS27C240 and TMS27PC240 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active ICC supply current can be reduced from 50 mA to 1 mA by applying a high TTL input on E and to
100
µA by applying a high CMOS input on E. In this mode all outputs are in the high-impedance state.
erasure ( TMS27C240)
Before programming, the TMS27C240 is erased by exposing the chip through the transparent lid to a high
intensity ultraviolet light (wavelength 2537 Å). The recommended minimum exposure dose (UV intensity
×
exposure time) is 15-W
⋅s/cm2. A 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The lamp
should be located about 2.5 cm above the chip during erasure. After erasure, all bits are in the high state. It
should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using
the TMS27C240, the window should be covered with an opaque label.
initializing ( TMS27PC240)
The one-time programmable TMS27PC240 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The TMS27C240 and TMS27PC240 are programmed by using the SNAP! Pulse programming algorithm. The
programming sequence is shown in the SNAP! Pulse programming flow chart, shown in Figure 1.
The initial setup is VPP = 13 V, VCC = 6.5 V, E = VIH, and G = VIH. Once the initial location is selected, the data
is presented in parallel (eight bits) on pins DQ0 through DQ15. Once addresses and data are stable, the
programming mode is achieved when E is pulsed low ( VIL) with a pulse duration of tw(PGM). Every location is
programmed only once before going to interactive mode.
In the interactive mode, the word is verified at VPP = 13 V, VCC = 6.5 V, E = VIH, and G = VIL. If the correct data
is not read, the programming is performed by pulling E low with a pulse duration of tw(PGM). This sequence of
verification and programming is performed up to a maximum of 10 times. When the device is fully programmed,
all bytes are verified with VCC = VPP = 5 V ± 10%.
program inhibit
Programming can be inhibited by maintaining a high level input on the E and G pins.
program verify
Programmed bits can be verified with VPP = 13 V when G = VIL and E = VIH.


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