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TMS27C240-10JL Datasheet(PDF) 3 Page - Texas Instruments

Part No. TMS27C240-10JL
Description  TMS27C240 262144 BY 16-BIT UV ERASABLE TM27PC240 262144 BY 16-BIT
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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TMS27C240-10JL Datasheet(HTML) 3 Page - Texas Instruments

 
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TMS27C240 262144 BY 16BIT UV ERASABLE
TMS27PC240 262144 BY 16BIT
PROGRAMMABLE READONLY MEMORIES
SMLS240D− NOVEMBER 1990 − REVISED SEPTEMBER 1997
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
description (continued)
The TMS27PC240 OTP PROM is offered in a 44-lead plastic leaded chip carrier package using 1,25-mm
(50-mil) lead spacing ( FN suffix). The TMS27PC240 is offered with two choices of temperature ranges of 0
°C
to 70
°C (FNL suffix) and −40°C to 85°C (FNE suffix). See Table 1.
Table 1. Temperature Range Suffixes
SUFFIX FOR OPERATING FREE-
AIR TEMPERATURE RANGES
0
°C TO 70°C
−40
°C TO 85°C
TMS27C240-XXX
JL
JE
TMS27PC240-XXX
FNL
FNE
These EPROMs and OTP PROMs operate from a single 5-V supply ( in the read mode), and they are ideal for
use in microprocessor-based systems. One other (13 V) supply is needed for programming . All programming
signals are TTL level. For programming outside the system, existing EPROM programmers can be used.
operation
The eight modes of operation for the TMS27C240 and TMS27PC240 are listed in Table 2. The read mode
requires a single 5-V supply. All inputs are TTL level except for VPP during programming (13 V for SNAP! Pulse),
and 12 V on A9 for the signature mode.
Table 2. Operation Modes
FUNCTION †
E
G
VPP
VCC
A9
A0
I/O
Read
VIL
VIL
VCC
VCC
X
X
DQ0 − DQ7
DQ8 − DQ15
Output Disable
VIL
VIH
VCC
VCC
X
X
Hi-Z
Standby
VIH
X
VCC
VCC
X
X
Hi-Z
Programming
VIL
VIH
VPP
VCC
X
X
Data In
Verify
VIH
VIL
VPP
VCC
X
X
Data Out
Program Inhibit
VIH
VIH
VPP
VCC
X
X
Hi-Z
Signature Mode (Mfg)
VIL
VIL
VCC
VCC
VH‡
VIL
Manufacturer’s
Code
0097
Signature Mode (Device)
VIL
VIL
VCC
VCC
VH‡
VIH
Device Code
0030
† X can be VIL or VIH.
‡ VH = 12 V ± 0.5 V.
read / output disable
When the outputs of two or more TMS27C240s or TMS27PC240s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins.


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