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TLV5617AIDR Datasheet(PDF) 10 Page - Texas Instruments |
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TLV5617AIDR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 20 page TLV5617A 2.7-V TO 5.5-V LOW-POWER DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN SLAS234F – JULY 1999 – REVISED JULY 2002 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION general function The TLV5617A is a dual 10-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial interface, speed and power-down control logic, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by the reference) is given by: 2REF CODE 2n [V] Where REF is the reference voltage and CODE is the digital input value within the range of 010 to 2n–1, where n=10 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format section. A power-on reset initially resets the internal latches to a defined state (all bits zero). serial interface A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word. Figure 12 shows examples of how to connect the TLV5617A to TMS320, SPI, and Microwire. TMS320 DSP FSX CLKX DX TLV5617A SCLK DIN CS SPI I/O SCK MOSI TLV5617A SCLK DIN CS Microwire I/O SK SO TLV5617A SCLK DIN CS Figure 12. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire) two write operations must be performed to program the TLV5617A. After the write operation(s), the holding registers or the control register of the DAC update automatically on the rising CS edge, ending the write cycle to the DAC. Note: After transfer of the LSB during a data or control write cycle, one additional rising edge on SCLK is required to reset the internal state machine. This edge can occur when CS is high or low, but must occur before the next falling CS edge that begins the following write cycle. Refer to the timing diagram for more information. serial clock frequency and update rate The maximum serial clock frequency is given by: f sclkmax + 1 t whmin ) twlmin + 20 MHz The maximum update rate is: f updatemax + 1 16 t whmin ) twlmin + 1.25 MHz Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the TLV5617A should also be considered. |
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