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SAA7154E Datasheet(PDF) 34 Page - NXP Semiconductors |
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SAA7154E Datasheet(HTML) 34 Page - NXP Semiconductors |
34 / 90 page SAA7154E_SAA7154H_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 6 December 2007 34 of 90 NXP Semiconductors SAA7154E; SAA7154H Multistandard video decoder with comb filter 7.14.1 Analog terminals The SAA7154E; SAA7154H has 16 analog inputs AI41 to AI44, AI31 to AI34, AI21 to AI24 and AI11 to AI14 for composite video CVBS or s-video Y/C signal pairs or component video input signals RGB plus separate sync (or Y-PB-PR plus separate sync). Component signals with e.g. sync-on-Y or sync-on-green are also supported; they are fed to two ADC channels, one for the video content, the other for sync conversion. Additionally, there are four differential reference inputs which must be connected to ground through a capacitor equivalent to the decoupling capacitors at the 16 inputs. There are no peripheral components required other than these decoupling capacitors and termination resistors, one set per connected input signal. When using the OSD feature in combination with the SAA5697HL, the analog pins AI22, AI32, AI42 and AI44 are reserved for analog OSD and can not be used for other input sources. Clamp and gain control for the four ADCs are also integrated. Two analog video outputs (pins AOUT1 and AOUT2) are provided. They can be used for analog output for one of the input signals. In addition, pin AOUT2 can output the sum of two analog input signals. This can be used for CVBS generation from an Y/C signal. 7.14.2 Audio clock signals The SAA7154E; SAA7154H also synchronizes the audio clock and sampling rate to the video frame rate through a very slow PLL. This ensures that multimedia capture and compression processes always gather the same predefined number of samples per video frame. An audio master clock AMCLK and two divided clocks ASCLK and ALRCLK are generated: • ASCLK: can be used as audio serial clock • ALRCLK: audio left/right channel clock. The ratios are programmable. Table 8. Analog pin description Pin I/O Description Control through AI11 to AI14 I analog video signal inputs, e.g. 16 CVBS signals or eight Y/C pairs or four RGB plus separate sync (or Y-PB-PR plus separate sync) signal groups can be connected simultaneously to this device; many combinations are possible MODE[5:0] AI21 to AI24 AI31 to AI34 AI41 to AI44 AOUT1 O analog video output 1 AOSL1[3:0] AOUT2 O analog video output 2 AOSL2[1:0], AOSL2A[1:0] and AOSL2B[1:0] AI1D, AI2D, AI3D and AI4D I analog reference pins for differential ADC operation; connect to ground through 47 Ω/22 nF - |
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