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LP62S2048X-10LT Datasheet(PDF) 2 Page - AMIC Technology |
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LP62S2048X-10LT Datasheet(HTML) 2 Page - AMIC Technology |
2 / 17 page LP62S2048-T Series (August, 2001, Version 1.0) 2 AMIC Technology, Inc. Block Diagram ROW DECODER 1024 X 2048 MEMORY ARRAY INPUT DATA CIRCUIT COLUMN I/O CONTROL CIRCUIT CE2 CE1 WE I/O8 I/O1 A17 A16 A15 A0 VCC GND OE Pin Description - SOP Pin No. Symbol Description 1 - 12, 23, 25 - 28, 31 A0 - A17 Address Inputs 13 - 15, 17 - 21 I/O1 - I/O8 Data Input/Outputs 16 GND Ground 22 CE1 Chip Enable 24 OE Output Enable 29 WE Write Enable 30 CE2 Chip Enable 32 VCC Power Supply Pin Descriptions - TSOP/TSSOP Pin No. Symbol Description 1 - 4, 7, 9 - 20, 31 A0 - A17 Address Inputs 5 WE Write Enable 6 CE2 Chip Enable 8 VCC Power Supply 9 NC No Connection 21 - 23, 25 - 29 I/O1 - I/O8 Data Input/Outputs 24 GND Ground 30 CE1 Chip Enable 32 OE Output Enable |
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