STM8S103K2M6TR datasheet(6/113 Pages) STMICROELECTRONICS

Part #	STM8S103K2M6TR

Description	Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash, data EEPROM,10-bit ADC, 3 timers, UART, SPI, I짼C

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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List of figures

Figure 1. Block diagram .........................................................................................................................10

Figure 2. Flash memory organization ....................................................................................................13

Figure 3. STM8S103Kx UFQFPN32/LQFP32 pinout .............................................................................19

Figure 4. STM8S103Fx TSSOP20/SO20 pinout ....................................................................................22

Figure 5. STM8S103Fx UFQFPN20-pin pinout .....................................................................................23

Figure 6. Memory map ...........................................................................................................................26

Figure 7. Pin loading conditions .............................................................................................................48

Figure 8. Pin input voltage .....................................................................................................................49

Figure 9. fCPUmax versus VDD ................................................................................................................52

Figure 10. External capacitor CEXT .......................................................................................................53

Figure 11. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz .............................................61

Figure 12. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V ....................................................61

Figure 13. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................62

Figure 14. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz ..............................................62

Figure 15. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V .....................................................63

Figure 16. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz .................................................................63

Figure 17. HSE external clocksource .....................................................................................................64

Figure 18. HSE oscillator circuit diagram ...............................................................................................65

Figure 19. Typical HSI accuracy at VDD = 5 V vs 5 temperatures ..........................................................66

Figure 20. Typical HSI frequency variation vs VDD @ 4 temperatures ..................................................67

Figure 21. Typical LSI frequency variation vs VDD @ 4 temperatures ...................................................67

Figure 22. Typical VIL and VIH vs VDD @ 4 temperatures ......................................................................70

Figure 23. Typical pull-up resistance vs VDD @ 4 temperatures ............................................................70

Figure 24. Typical pull-up current vs VDD @ 4 temperatures .................................................................71

Figure 25. Typ. VOL @ VDD = 5 V (standard ports) ................................................................................72

Figure 26. Typ. VOL @ VDD = 3.3 V (standard ports) .............................................................................73

Figure 27. Typ. VOL @ VDD = 5 V (true open drain ports) ......................................................................73

Figure 28. Typ. VOL @ VDD = 3.3 V (true open drain ports) ...................................................................74

Figure 29. Typ. VOL @ VDD = 5 V (high sink ports) ................................................................................74

Figure 30. Typ. VOL @ VDD = 3.3 V (high sink ports) .............................................................................75

Figure 31. Typ. VDD - VOH@ VDD = 5 V (standard ports) .......................................................................75

Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) ...................................................................76

Figure 33. Typ. VDD - VOH@ VDD = 5 V (high sink ports) .......................................................................76

Figure 34. Typ. VDD - VOH@ VDD = 3.3 V (high sink ports) ....................................................................77

Figure 35. Typical NRST VIL and VIH vs VDD @ 4 temperatures ...........................................................78

Figure 36. Typical NRST pull-up resistance vs VDD @ 4 temperatures .................................................78

Figure 37. Typical NRST pull-up current vs VDD @ 4 temperatures ......................................................79

Figure 38. Recommended reset pin protection ......................................................................................79

Figure 39. SPI timing diagram - slave mode and CPHA = 0 ..................................................................81

Figure 40. SPI timing diagram - slave mode and CPHA = 1 ..................................................................81

Figure 41. SPI timing diagram - master mode

(1)

...................................................................................82

Figure 42. Typical application with I

2C bus and timing diagram ............................................................86

Figure 43. ADC accuracy characteristics ...............................................................................................86

Figure 44. Typical application with ADC ................................................................................................87

Figure 45. 32-pin low profile quad flat package (7 x 7) ..........................................................................91

Figure 46. 32-lead, ultra thin, fine pitch quad flat no-lead package (5 x 5) ............................................93

Figure 47. 20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3) ................................94

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