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STM8S103F3M3TR Datasheet(PDF) 10 Page - STMicroelectronics |
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STM8S103F3M3TR Datasheet(HTML) 10 Page - STMicroelectronics |
10 / 113 page Block diagram 3 Figure 1: Block diagram XTAL 1-16 MHz RC int. 16 MHz RC int. 128 kHz STM8 core Debug/SWIM SPI UART1 16-bit general purpose AWU timer Reset block Reset POR BOR Clock controller Detector Clock to peripherals and core 8 Mbit/s LIN master Window WDG 8 Kbytes 640 bytes 1 Kbyte ADC1 4 CAPCOM Reset 400 Kbit/s Single wire debug interf. SPI emul. channels +3 program Flash 16-bit advanced control timer (TIM1) 8-bit basic timer data EEPROM RAM Up to Beeper 1/2/4 kHz beep Independent WDG (TIM4) 3 CAPCOM channels Up to complementary outputs timer (TIM2) Up to 5 channels I2C DocID15441 Rev 6 10/113 STM8S103K3 STM8S103F3 STM8S103F2 Block diagram |
Similar Part No. - STM8S103F3M3TR |
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