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STM32F103ZET7 Datasheet(PDF) 98 Page - STMicroelectronics

Part # STM32F103ZET7
Description  High-density performance line ARM-based 32-bit MCU
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F103ZET7 Datasheet(HTML) 98 Page - STMicroelectronics

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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
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Doc ID 14611 Rev 8
Table 54.
I2S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
DuCy(SCK)
I2S slave input clock duty
cycle
Slave mode
30
70
%
fCK
1/tc(CK)
I2S clock frequency
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
1.522
1.525
MHz
Slave mode
0
6.5
tr(CK)
tf(CK)
I2S clock rise and fall time
Capacitive load CL =50 pF
8
ns
tv(WS)
(1)
WS valid time
Master mode
3
th(WS)
(1)
WS hold time
Master mode
I2S2
2
I2S3
0
tsu(WS)
(1)
WS setup time
Slave mode
4
th(WS)
(1)
WS hold time
Slave mode
0
tw(CKH)
(1)
CK high and low time
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
312.5
tw(CKL)
(1)
345
tsu(SD_MR)
(1)
Data input setup time
Master receiver
I2S2
2
I2S3
6.5
tsu(SD_SR)
(1)
Data input setup time
Slave receiver
1.5
th(SD_MR)
(1)(2)
Data input hold time
Master receiver
0
th(SD_SR)
(1)(2)
Slave receiver
0.5
tv(SD_ST)
(1)(2)
Data output valid time
Slave transmitter (after enable
edge)
18
th(SD_ST)
(1)
Data output hold time
Slave transmitter (after enable
edge)
11
tv(SD_MT)
(1)(2)
Data output valid time
Master transmitter (after enable
edge)
3
th(SD_MT)
(1)
Data output hold time
Master transmitter (after enable
edge)
0
1.
Based on design simulation and/or characterization results, not tested in production.
2.
Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.


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