LP62S1024BU-55LLT datasheet(2/18 Pages) AMICC

Part #	LP62S1024BU-55LLT

Description	128K X 8 BIT LOW VOLTAGE CMOS SRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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LP62S1024B-T Series

Preliminary

128K X 8 BIT LOW VOLTAGE CMOS SRAM

PRELIMINARY

(October, 2002, Version 0.1)

1

AMIC Technology, Corp.

Features

General Description

n Power supply range: 2.7V to 3.6V

n Access times: 55/70 ns (max.)

n Current:

Very low power version: Operating: 30mA(max.)

Standby: 5uA (max.)

n Full static operation, no clock or refreshing required

n All inputs and outputs are directly TTL-compatible

n Common I/O using three-state output

n Output enable and two chip enable inputs for easy

application

n Data retention voltage: 2V (min.)

n Available in 32-pin SOP, TSOP, TSSOP (8 X 13.4mm)

forward type and 36-pin CSP packages

The LP62S1024B-T is a low operating current 1,048,576-

bit static random access memory organized as 131,072

words by 8 bits and operates on a low power voltage: 2.7V

to 3.6V. It is built using AMIC's high performance CMOS

process.

Inputs and three-state outputs are TTL compatible and

allow for direct interfacing with common system bus

structures.

Two chip enable inputs are provided for POWER-DOWN

and device enable and an output enable input is included

for easy interfacing.

Data retention is guaranteed at a power supply voltage as

low as 2V.

Product Family

Power Dissipation

Product Family

Operating

Temperature

VCC

Range

Speed

Data Retention

(ICCDR, Typ.)

Standby

(ISB1, Typ.)

Operating

(ICC2, Typ.)

Package

Type

LP62S1024B

-25

°C ~ +85°C 2.7V~3.6V

55ns / 70ns

0.05

µA

0.08

µA

1.5mA

32L SOP

32L TSOP

32L TSSOP

36B

µBGA

1. Typical values are measured at VCC = 3.0V, TA = 25

°C and not 100% tested.

2. Data retention current VCC = 2.0V.

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LP62S1024BU-55LLT Datasheet(PDF) 2 Page - AMIC Technology

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