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A8351601L-40 Datasheet(PDF) 38 Page - AMIC Technology

Part No. A8351601L-40
Description  Bar Code Reader
Download  44 Pages
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

A8351601L-40 Datasheet(HTML) 38 Page - AMIC Technology

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A8351601 Series
(July, 2002, Version 1.0)
37
AMIC Technology, Inc.
AC Characteristics (TA = -10
°C to + 70°C, VCC = 5V ± 10% or VCC = 3V ± 10%)
Symbol
Parameter
Min.
Max.
Unit
Program Memory Cycle
tAP
ALE Pulse Width
2tck – 20
1
-
ns
tALS
Address Valid to ALE Low
1tck
-
ns
tALH
Address Hold from ALE Low
1tck
-
ns
top
PSEN Pulse Width
3tck - 20
1
-
ns
tAO
ALE Low to
PSEN Low
1tck
-
ns
tOI
2
PSEN Low to Valid Instruction in
-
2tck
ns
tIDO
Input Instruction Hold after
PSEN High
-
1tck
ns
tIFO
Input Instruction Float after
PSEN High
-
1tck
ns
External Clock(VCC =5V
± 10% or VCC = 3V ± 10%)
fOPER
Clock Frequency (VCC =5V
± 10%)
0
40
MHZ
fOPER
Clock Frequency (VCC =3V
± 10%)
0
16
MHZ
tCK
3
Clock Period
25
-
ns
tCKH
4
Clock High Time
10
-
ns
tCKL
4
Clock Low Time
10
-
ns
Data Memory Cycle
tPR
RD Pulse Width
6tck - 20
1
-
ns
tPD
RD Low to Valid Data in
-
4tck
ns
tDHR
Data Hold from
RD High
0
2tck
ns
tDFR
Data Float from
RD High
0
2tck
ns
tAR
ALE Low to
RD Low
3tck
3tck + 20
1
ns
tWP
WR Pulse Width
6tck - 20
1
-
ns
tDS
Valid Data to
WR Low
1tck
-
ns
tDHW
Data Hold from
WR High
1tck
-
ns
tAW
ALE Low to
WR Low
3tck
3tck + 20
1
ns
Serial Port Cycle
tSCK
Serial Port Clock
12tck
-
ns
tKI
Clock Rising Edge to Valid Input Data
-
11tck
ns
tIKH
Input Data to Serial Clock Rising Clock Hold Time
0
-
ns
tOKS
Output Data to Serial Clock Rising Edge Setup Time
11tck
-
ns
tOKH
Output Data to Serial Clock Rising Edge Hold Time
1tck
-
ns
1.
This 20 ns is due to buffer driving delay and wire loading.
2.
Instruction cycle time is 12 tck.
3.
tck = 1/ foper
4.
There are no duty cycle requirements on the XTAL1 input.


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