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A8351601L-40 Datasheet(PDF) 31 Page - AMIC Technology

Part No. A8351601L-40
Description  Bar Code Reader
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

A8351601L-40 Datasheet(HTML) 31 Page - AMIC Technology

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A8351601 Series
(July, 2002, Version 1.0)
30
AMIC Technology, Inc.
Thus, the processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the appropriate
servicing routine. In some cases it also clears the flag that
generated the interrupt, and in other cases it does not. It
never clears the Serial Port or Timer 2 flags.
This must be done in the user's software. The processor
clears an external interrupt flag (IE0 or IE1) only if it was
transition-activated.
The
hardware-generated
LCALL
pushes the contents of the Program Counter onto the stack
(but it does not save the PSW) and reloads the PC with an
address that depends on the source of the interrupt being
serviced, as follows:
Interrupt
Source
Interrupt
Request Bits
Cleared by
Hardware
Vector
Address
INT0
IE0
No (level)
Yes (trans.)
0003H
Timer 0
TF0
Yes
000BH
INT1
IE1
No (level)
Yes (trans.)
0013H
Timer 1
TF1
Yes
001BH
Serial Port
RI, TI
No
0023H
Timer 2
TF2, EXF2
No
002BH
System
Reset
RST
0000H
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.
Note that a simple RET instruction would also have
returned execution to the interrupted program, but it would
have left the interrupt control system thinking an interrupt
was still in progress.
Interrupt
Flag
SFR Register and
Bit Position
External 0
IE0
TCON.1
External 1
IE1
TCON.3
Timer 1
TF1
TCON.7
Timer 0
TF0
TCON.5
Serial Port
TI
SCON.1
Serial Port
TF2
RI
T2CON.7
SCON.0 Timer 2
Timer 2
EXF2
T2CON.6
When an interrupt is accepted the following action occurs:
1. The current instruction completes operation.
2. The PC is saved on the stack.
3. The current interrupt status is saved internally.
4. Interrupts are blocked at the level of the interrupts.
5. The PC is loaded with the vector address of the ISR
(interrupts service routine).
6. The ISR executes.
The ISR executes and takes action in response to the
interrupt. The ISR finishes with RETI (return from interrupt)
instruction. This retrieves the old value of the PC from the
stack and restores the old interrupt status. Execution of the
main program continues where it left off.
External Interrupts
The external sources can be programmed to be level-
activated or transition-activated by setting or clearing bit
IT1 or IT0 in Register TCON. If ITx= 0, external interrupt x
is triggered by a detected low at the INTx pin. If ITx = 1,
external interrupt x is edge-triggered. In this mode if
successive samples of the INTx pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEx
in TCON is set. Flag bit IEx then requests the interrupt.
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at least
12 oscillator periods to ensure sampling. If the external
interrupt is transition-activated, the external source has to
hold the request pin high for at least one machine cycle,
and then hold it low for at least one machine cycle to
ensure that the transition is seen so that interrupt request
flag IEx will be set. IEx will be automatically cleared by the
CPU when the service routine is called.
If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then the external source
must deactivate the request before the interrupt service
routine is completed, or else another interrupt will be
generated.
Response Time
The INT0 and INT1 levels are inverted and latched into
the interrupt flags IE0 and IE1 at S5P2 of every machine
cycle. Similarly, the Timer 2 flag EXF2 and the Serial Port
flags RI and TI are set at S5P2. The values are not actually
polled by the circuitry until the next machine cycle.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle. However,
the Timer 2 flag TF2 is set at S2P2 and is polled in the
same cycle in which the timer overflows.


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