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A8351601L-40 Datasheet(PDF) 12 Page - AMIC Technology

Part No. A8351601L-40
Description  Bar Code Reader
Download  44 Pages
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

A8351601L-40 Datasheet(HTML) 12 Page - AMIC Technology

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A8351601 Series
(July, 2002, Version 1.0)
11
AMIC Technology, Inc.
T2CON: (continued)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/ T2
CP/RL2
Register Description:
EXEN2
T2CON.3
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port, EXEN2 = 0
causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
Software START/STOP control for Timer 2. A logic 1 starts the Timer.
C/ T2
T2CON.1
Timer or Counter select. 0 = Internal Timer. 1 = External Event Counter (triggered by falling
edge).
CP/RL2
T2CON.0
Capture/Reload flag. When set, captures occur on negative transitions at T2EX if EXEN2
=1. When cleared, auto-reloads occur either with Timer 2 overflows or negative transitions
at T2EX when EXEN2=1. When either RCLK=1 or TCLK=1, this bit is ignored and the Timer
is forced to auto-reload on Timer 2 overflow.
Notes:
Timer 2 Operating Modes
RCLK + TCLK
CP/RL2
TR2
MODE
0
0
1
16-Bit Auto-Reload
0
1
1
16-Bit Capture
1
X
1
Baud Rate Generator
ADD(A1H):
Extra Additional Register. Not Bit Addressable.
7
6
5
4
3
2
1
0
-
-
Delay2
Delay1
Delay0
T2EXREV
DF
RAMDIS
Register Description:
-
Not implemented, reserve for future use.
-
Not implemented, reserve for future use.
D2
PWM3 delay control bit.
D1
PWM3 delay control bit.
D0
PWM3 delay control bit.
T2EXREV
T2EX reverse control bit. Set/Cleared by software specify T2EX pin reverse/no reverse.
DF
Double system frequency control bit. Set/Cleared by software specify Xtal frequency *2 / Xtal frequency.
RAMDIS
Build in 8K bytes SRAM enable/disable control bit. Set/Cleared by software specify
Enable/disable build in 8K bytes SRAM.
Bit <5:3>
0
1
2
3
4
5
6
7
Delay
4 CLK
5 CLK
6 CLK
7 CLK
8 CLK
9 CLK
10 CLK
11 CLK
(D2, D1, D0) controlled the delay time of PWM3 after PWM1 change.


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