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A8351601L-40 Datasheet(PDF) 11 Page - AMIC Technology

Part No. A8351601L-40
Description  Bar Code Reader
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

A8351601L-40 Datasheet(HTML) 11 Page - AMIC Technology

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A8351601 Series
(July, 2002, Version 1.0)
10
AMIC Technology, Inc.
Note 1:
M1
M0
Operating mode
0
0
Mode 0. (13-bit Timer)
0
1
Mode 1. (16-bit Timer/Counter)
1
0
Mode 2. (8-bit auto-load Timer/Counter)
1
1
Mode 3. (Splits Timer 0 into TL0 and TH0. TL0 is an 8-bit Timer/
Counter controller by the standard Timer 0 control bits. TH0 is an
8-bit Timer and is controlled by Timer 1 control bits.)
1
1
Mode 3. (Timer/Counter 1 stopped).
SCON:
Serial Port Control Register. Bit Addressable.
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Register Description:
SM0
SCON.7
Serial port mode specifically. (1)
SM1
SCON.6
Serial port mode specifically. (1)
SM2
SCON.5
Enable the multiprocessor communication feature in mode 2 and 3. In mode 2 or 3, if SM2
is set to 1 then RI will not be activated if the received 9
th data bit (RB8) is 0. In mode 1, if
SM2=1 then RI will not be activated if valid stop bit was not received. In mode 0, SM2
should be 0.
REN
SCON.4
Set/Cleared by software to Enable/Disable reception.
TB8
SCON.3
The 9th bit that will be transmitted in mode 2 and 3. Set/Cleared by software.
RB8
SCON.2
In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2=0, RB8 is
the stop bit that was received. In mode 0, RB8 is not used.
TI
SCON.1
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the
beginning of the stop bit in the other modes. Must be cleared by software.
RI
SCON.0
Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway
through the stop bit time in the other modes (except see SM2). Must be cleared by
software.
Note:
SM0
SM1
MODE
Description
Baud rate
0
0
0
Shift register
Fosc/12
0
1
1
8-bit UART
Variable
1
0
2
9-bit UART
Fosc/64 or Fosc/32
1
1
3
9-bit UART
Variable
T2CON:
Timer/Counter 2 Control Register. Bit Addressable.
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/ T2
CP/RL2
Register Description:
TF2
T2CON.7
Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when
either RCLK = 1 or TCLK = 1.
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative transition
on T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 causes the CPU to
vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK
T2CON.5
Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the
receive clock.
TCLK
T2CON.4
Transmit clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its
transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the
transmit clock.


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