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A8351601L-40 Datasheet(PDF) 10 Page - AMIC Technology

Part No. A8351601L-40
Description  Bar Code Reader
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

A8351601L-40 Datasheet(HTML) 10 Page - AMIC Technology

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A8351601 Series
(July, 2002, Version 1.0)
9
AMIC Technology, Inc.
IP:
Interrupt Priority Register. Bit Addressable.
7
6
5
4
3
2
1
0
-
-
PT2
PS
PT1
PX1
PT0
PX0
Register Description:
-
IP.7
Not implemented, reserve for future use (3)
-
IP.6
Not implemented, reserve for future use (3)
PT2
IP.5
Defines Timer 2 interrupt priority level
PS
IP.4
Defines Serial Port interrupt priority level
PT1
IP.3
Defines Timer 1 interrupt priority level
PX1
IP.2
Defines External Interrupt 1 priority level
PT0
IP.1
Defines Timer 0 interrupt priority level
PX0
IP.0
Defines External Interrupt 0 priority level
Notes:
1. In order to assign higher priority to an interrupt the corresponding bit in the IP register must be set to 1. While an
interrupt service is in progress, it cannot be interrupted by a lower or same level interrupt.
2. Priority within level is only to resolve simultaneous requests of the same priority level. From high to low, interrupt sources
are listed below:
IE0 > TF0 > IE1 > TF1 > RI or TI > TF2 or EXF2
3. User software should not write 1s to reserved bits. These bits may be used in future products to invoke new features.
TCON:
Timer/Counter Control Register. Bit Addressable.
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Register Description:
TF1
IP.7
Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 overflows.
Cleared by hardware as processor vectors to the interrupt service routine.
TR1
IP.6
Timer 1 run control bit. Set/Cleared by software to turn Timer/Counter 1 ON/OFF.
TF0
IP.5
Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows.
Cleared by hardware as processor vectors to the interrupt service routine.
TR0
IP.4
Timer 0 run control bit. Set/Cleared by software to turn Timer/Counter 0 ON/OFF.
IE1
IP.3
External Interrupt 1 edge flag. Set by hardware when the External Interrupt edge is
detected. Cleared by hardware when interrupt is processed.
IT1
IP.2
Interrupt 1 type control bit. Set/Cleared by software specify falling edge/low level triggered
External Interrupt.
IE0
IP.1
External Interrupt 0 edge flag. Set by hardware when the External Interrupt edge is
detected. Cleared by hardware when interrupt is processed.
IT0
IP.0
Interrupt 0 type control bit. Set/Cleared by software specify falling edge/low level triggered
External Interrupt.
TMOD:
Timer/Counter Mode Control Register. Not Bit Addressable.
Timer 1
Timer 0
GATE
C/ T
M1
M0
GATE
C/ T
M1
M0
GATE
When TRx (in TCON) is set and GATE=1, TIMER/COUNTERx will run only while INTx pin is high (hardware
control). When GATE=0, TIMER/COUNTERx will run only while TRx=1 (software control).
C/ T
Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for Counter
operation (input from Tx input pin).
M1
Mode selector bit. (1)
M0
Mode selector bit. (1)


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