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A8351601L-40 Datasheet(PDF) 8 Page - AMIC Technology

Part No. A8351601L-40
Description  Bar Code Reader
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

A8351601L-40 Datasheet(HTML) 8 Page - AMIC Technology

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A8351601 Series
(July, 2002, Version 1.0)
7
AMIC Technology, Inc.
Program Status Word (PSW). The PSW register contains
program status information.
Stack Pointer (SP)
The Stack Pointer Register is eight bits wide. It is
incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in on-chip
RAM, the Stack Pointer is initialized to 07H after a reset.
This causes the stack to begin at location 08H.
Data Pointer (DPTR)
The Data Pointer consists of a high byte (DPH) and a low
byte (DPL). Its function is to hold a 16-bit address. It may be
manipulated as a 16-bit register or as two independent 8-bit
registers.
Ports 0 To 3
P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and
3, respectively.
Serial Data Buffer (SBUF)
The Serial Data Buffer is actually two separate registers, a
transmit buffer and a receive buffer register. When data is
moved to SBUF, it goes to the transmit buffer, where it is
held for serial transmission. (Moving a byte to SBUF
initiates the transmission.) When data is moved from SBUF,
it comes from the receive buffer.
Timer Registers
Register pairs (TH0, TL0), (TH1, TL1), and (TH2, TL2) are
the 16-bit Counter registers for Timer/Counters 0, 1, and 2,
respectively.
Capture Registers
The register pair (RCAP2H, RCAP2L) are the Capture
registers for the Timer 2 Capture Mode. In this mode, in
response to a transition at the A8351601's T2EX pin, TH2
and TL2 are copied into RCAP2H and RCAP2L. Timer 2
also has a 16-bit auto-reload mode, and RCAP2H and
RCAP2L hold the reload value for this mode.
Control Registers
Special Function Registers IP, IE, TMOD, TCON, T2CON,
SCON, and PCON contain control and status bits for the
interrupt system, the Timer/Counters, and the serial port.
They are described in later sections of this chapter.
The detail description of each bit is as follows:
PSW:
Program Status Word. Bit Addressable.
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
-
P
Register Description:
CY
PSW.7
Carry flag.
AC
PSW.6
Auxiliary carry flag.
F0
PSW.5
Flag 0 available to the user for general purpose.
RS1
PSW.4
Register bank selector bit 1. (1)
RS0
PSW.3
Register bank selector bit 0. (1)
OV
PSW.2
Overflow flag.
-
PSW.1
Usable as a general purpose flag
P
PSW.0
Parity flag. Set/Clear by hardware each instruction cycle to indicate an odd/even number of
"1" bits in the accumulator.
Note:
1. The value presented by RS0 and RS1 selects the corresponding register bank.
RS1
RS0
Register Bank
Address
0
0
0
00H-07H
0
1
1
08H-0FH
1
0
2
10H-17H
1
1
3
18H-1FH


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