A83516 Series

PRELIMINARY

(November, 1998, Version 0.0)

4

AMIC Technology, Inc.

XTAL 2

XTAL 1

C1

C2

C1,C2 = 30pF ± 10pF for Crystals

Figure 1. Oscillator Connections

XTAL 2

XTAL 1

N/C

EXTERNAL

OSCILLATOR

SIGNAL

Figure 2. External Clock Drive configuration

Functional Description

The A83516 is a high speed 8-bit microcontroller. The architecture consists of a core controller, four general purposes I/O

ports, 256 bytes RAM internal register, 64K bytes ROM and a serial port.

This microcontroller supports 111 opcodes and executes instructions in 12 clock/machine cycle. It can reference both a

64K program address space and a 64K data storage space.

Timer/Counter 0, 1 and 2

Timer 0,1 and 2 each consist of two 8-bit data registers.

These are called TL0 and TH0 for Timer 0. TL1 and TH1

for Timer 1, and TL2 and TH2 for Timer 2. The TMOD

and TCON registers support control function for Timer 0

and Timer 1. The T2CON register provides control

function for Timer 2. When operating reload/capture

mode, RCAP2H and RCAP2L will be used.

Interrupt

The A83516 provides 6 interrupt modes. These consist

of 2 external interrupts, 3 internal interrupts and a serial

port interrupt.

The enable/disable interrupt is controlled by IE register in

SFR.

The priority of interrupts is controlled by IP register in

SFR.

Serial Port Transfer

The A83516 provides a full duplex serial transfer

function.

This function is controlled by SCON register in SFR.

And the data is storaged in SBUF register during

transmitting and receiving.

Oscillator Characteristics

The oscillator connections are shown as Figure 1. And

Figure 2. When quartz crystal is used, C1 and C2 are

30pF shown in Figure 1. When external clock is used,

the internal clock will be gotten through a divide-by-two

flip-flop. When starting up, the input loading for XTAL1

pin is 100pF. This is due to interaction between the

amplifier and its feedback capacitance interaction. After

the capacitance will not exceed 20pF.

Power Reduce Mode

IDLE Mode

It is executed by IDLE bit of PCON register in SFR. In

idle mode, the clock to microcontroller core is stopped.

The status in microcontroller core and I/O data are kept.

The microcontroller will stop idle status when either a

reset or an interrupt occurs.

POWER-DOWN Mode

It is executed by PD bit of PCON register in SFR. In

power-down mode, the oscillator clock will stop. The

data in RAM and status in SFR will be kept. The only

way to exit power-down mode is to reset this chip.

RESET

The external reset signal must be held high for at least

two machine cycles during the oscillator running.

After reset, the ports are held high, SP register to 07H,

all of the other SFR registers except SBUF to 00H, and

SBUF is not reset.