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A8351601 Datasheet(PDF) 5 Page - AMIC Technology

Part No. A8351601
Description  Bar Code Reader
Download  44 Pages
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Maker  AMICC [AMIC Technology]
Homepage  http://www.amictechnology.com
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A8351601 Datasheet(HTML) 5 Page - AMIC Technology

 
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A8351601 Series
(July, 2002, Version 1.0)
4
AMIC Technology, Inc.
Pin Description
Pin No.
Symbol
P-DIP
PLCC
QFP
I/O
Description
ALE
30
33
27
O
Address Latch Enable: Output pulse for latching the low
byte of the address during an address to the external
memory. In normal operation, ALE is emitted at a constant
rate of 1/6 the oscillator frequency, and can be used for
external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory.
EA
31
35
29
I
External Access enable: EA must be externally held low
to enable the device to fetch code from external program
memory locations 0000H to FFFFH. If EA is held high, the
device executes from internal program memory.
P0.0-P0.7
32-39
36-43
30-37
I/O
Port 0: Port 0 is an 8-bit bidirectional I/O port with internal
pullups. Port 0 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. Port
0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory.
1-8
2-9
40-44
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will source
current
because
of
the
internal
pullups.
(See
DC
Characteristics: IIL).
The Port 1 output buffers can sink/source four TTL inputs.
1
2
40
I
T2 (P1.0): Timer/Counter 2 external count input.
P1.0-P1.7
2
3
41
I
T2EX (P1.1): Timer/Counter 2 trigger input.
P2.0-P2.7
21-28
24-31
18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. As
inputs, Port 2 pins that are externally pulled low will source
current
because
of
the
internal
pullups.
(See
DC
Characteristics: IIL).
Port 2 emits the high order address byte during fetches
from external program memory and during accesses to
external data memory that used 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal
pullups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ Ri [i = 0, 1]),
Port 2 emits the contents of the P2 Special Function
Register.
Port 2 also receives the high-order bits and some control
signals during ROM verification.


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