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SN74LV373DW Datasheet(PDF) 4 Page - Texas Instruments |
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SN74LV373DW Datasheet(HTML) 4 Page - Texas Instruments |
4 / 7 page SN54LV373, SN74LV373 OCTAL TRANSPARENT DTYPE LATCHES WITH 3STATE OUTPUTS SCLS196C − FEBRUARY 1993 − REVISED APRIL 1996 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN54LV373 VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT MIN MAX MIN MAX MIN MAX UNIT tw Pulse duration, LE high 10 10 8 ns tsu Setup time, data before LE ↓ High or low 4 6 6 ns th Hold time, data after LE ↓ High or low 6 6 6 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN74LV373 VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT MIN MAX MIN MAX MIN MAX UNIT tw Pulse duration, LE high 10 10 8 ns tsu Setup time, data before LE ↓ High or low 4 6 6 ns th Hold time, data after LE ↓ High or low 6 6 6 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM TO SN54LV373 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT PARAMETER (INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX MIN MAX UNIT tpd D Q 8 16 11 22 28 ns tpd LE Q 11 19 15 25 26 ns ten OE Q 15 23 15 27 28 ns tdis OE Q 15 23 15 27 28 ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM TO SN74LV373 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V UNIT PARAMETER (INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX MIN MAX UNIT tpd D Q 8 16 11 22 28 ns tpd LE Q 11 19 15 25 26 ns ten OE Q 15 23 15 27 28 ns tdis OE Q 15 23 15 27 28 ns operating characteristics, TA = 25°C PARAMETER TEST CONDITIONS VCC TYP UNIT Outputs enabled 3.3 V 47 Cpd Power dissipation capacitance per latch Outputs disabled CL = 50 pF, f = 10 MHz 3.3 V 29 pF Cpd Power dissipation capacitance per latch Outputs enabled CL = 50 pF, f = 10 MHz 5 V 112 pF Outputs disabled 5 V 62 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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