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L9D232M64SBG5 Datasheet(PDF) 93 Page - LOGIC Devices Incorporated |
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L9D232M64SBG5 Datasheet(HTML) 93 Page - LOGIC Devices Incorporated |
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93 / 115 page  CK1 CK# Command NOP REF Address CKE1 Valid DQ DM DQS#, DQS NOP 4 t RP8 t CH t CL t CK1 t CK1 t XSNR2, 5, 10 t ISXR2 Enter self refresh mode (synchronous) Exit self refresh mode (asynchronous) T0 T1 Ta2 Ta1 Don’t Care Ta0 Tc0 Tb0 t XSRD2, 7 Valid 5 NOP 4 t CKE (MIN) 9 T2 ODT 6 t AOFD/ tAOFPD 6 Td0 Valid 7 Valid 5 Indicates a break in time scale tIH tIH t CKE3 Notes: 1. Clock must be stable and meeting tCK specifications at least 1 × tCK after entering self refresh mode and at least 1 × tCK prior to exiting self refresh mode. 2. Self refresh exit is asynchronous; however, t XSNR and tXSRD timing starts at the first ris- ing clock edge where CKE HIGH satisfies tISXR. 3. CKE must stay HIGH until tXSRD is met; however, if self refresh is being re-entered, CKE may go back LOW after tXSNR is satisfied. 4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0, which allows any nonREAD command. 5. tXSNR is required before any nonREAD command can be applied. 6. ODT must be disabled and R TT off ( tAOFD and tAOFPD have been satisfied) prior to enter- ing self refresh at state T1. 7. tXSRD (200 cycles of CK) is required before a READ command can be applied at state Td0. 8. Device must be in the all banks idle state prior to entering self refresh mode. 9. After self refresh has been entered, tCKE (MIN) must be satisfied prior to exiting self refresh. 10. Upon exiting SELF REFRESH, ODT must remain LOW until tXSRD is satisfied. LOGIC Devices Incorporated www.logicdevices.com September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E 93 2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD) L9D232M64SBG5 L9D232M72SBG5 L9D232M80SBG5 L9D264M64SBG5 L9D264M72SBG5 L9D264M80SBG5 High Performance, Integrated Memory Module Product t t meet t t t t SELF REFRESH FIGURE 61 - SELF REFRESH |
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