A62S6316G-70SI datasheet(11/15 Pages) AMICC

11 / 15 page

A62S6316 Series

PRELIMINARY

(August, 2002, Version 0.5)

10

AMIC Technology, Inc.

Timing Waveforms (continued)

Write Cycle 3

(Byte Enable Controlled)

tWC

tAW

Address

DATA IN

DATA OUT

WE

HB, LB

CE

tWR3

tCW

tBW2

tAS1

tWP

tDW

tDH

tOW

tWHZ4

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ).

3. tWR is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle.

4. OE level is high or low.

5. Transition is measured

±500mV from steady state. This parameter is sampled and not 100% tested.

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