A62S8308M-55SI datasheet(6/17 Pages) AMICC

Part #	A62S8308M-55SI

Description	256K X 8 BIT LOW VOLTAGE CMOS SRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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A62S8308 Series

PRELIMINARY

(March, 2001, Version 0.2)

5

AMIC Technology, Inc.

AC Characteristics (TA = 0

°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.6V)

Symbol

Parameter

A62S8308-55S/SI

(VCC = 3.0V to 3.6V)

A62S8308-70S/SI

(VCC = 2.7V to 3.6V)

Unit

Min.

Max.

Min.

Max.

Read Cycle

tRC

Read Cycle Time

55

-

70

-

ns

tAA

Address Access Time

-

55

-

70

ns

tACE1

Chip Enable Access Time

CE1

-

55

-

70

ns

tACE2

CE2

-

55

-

70

ns

tOE

Output Enable to Output Valid

-

30

-

35

ns

tCLZ1

Chip Enable to Output in Low Z

CE1

10

-

10

-

ns

tCLZ2

CE2

10

-

10

-

ns

tOLZ

Output Enable to Output in Low Z

5

-

5

-

ns

tCHZ1

Chip Disable to Output in High Z

CE1

0

20

0

25

ns

tCHZ2

CE2

0

20

0

25

ns

tOHZ

Output Disable to Output in High Z

0

20

0

25

ns

tOH

Output Hold from Address Change

5

-

10

-

ns

Read Cycle

tWC

Write Cycle Time

55

-

70

-

ns

tCW

Chip Enable to End of Write

50

-

60

-

ns

tAS

Address Setup Time

0

-

0

-

ns

tAW

Address Valid to End of Write

50

-

60

-

ns

tWP

Write Pulse Width

40

-

50

-

ns

tWR

Write Recovery Time

0

-

0

-

ns

tWHZ

Write to Output in High Z

0

25

0

25

ns

tDW

Data to Write Time Overlap

25

-

30

-

ns

tDH

Data Hold from Write Time

0

-

0

-

ns

tOW

Output Active from End of Write

5

-

5

-

ns

Notes:

tCHZ1, tCHZ2, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are

not referred to output voltage levels.

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