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SN74ACT72211L50RJR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74ACT72211L50RJR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 21 page SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L 512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9 SYNCHRONOUS FIRST IN, FIRST OUT MEMORIES SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 functional block diagram Input Register Dual-Port SRAM 512 × 9 or 1024 × 9 or 2048 × 9 or 4096 × 9 OE D0 − D8 WEN2 RS LD Synchronous Read Control Synchronous Write Control Reset Logic Status- Flag Logic Read Pointer Write Pointer Output Register Offset Registers WCLK REN2 REN1 RCLK Q0 − Q8 EF PAE PAF FF WEN1 † † 512 × 9 for the SN74ACT72211L; 1024 × 9 for the SN74ACT72221L; 2048 × 9 for the SN74ACT72231L; 4096 × 9 for the SN74ACT72241L |
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