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SN65HVD75DGK Datasheet(PDF) 5 Page - Texas Instruments |
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SN65HVD75DGK Datasheet(HTML) 5 Page - Texas Instruments |
5 / 30 page SN65HVD72 SN65HVD75 SN65HVD78 www.ti.com SLLSE11C – MARCH 2012 – REVISED SEPTEMBER 2013 SWITCHING CHARACTERISTICS 250 kbps device (HVD72) bit time ≥ 4 µs (over recommended operating conditions) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER Driver differential output rise/fall 0.3 0.7 1.2 µs tr, tf time RL = 54 Ω, CL = 50 pF See Figure 3 tPHL, tPLH Driver propagation delay 0.7 1 µs tSK(P) Driver pulse skew, |tPHL – tPLH| 0.2 µs tPHZ, tPLZ Driver disable time 0.1 0.4 µs See Figure 4 and Receiver enabled 0.5 1 µs Figure 5 tPZH, tPZL Driver enable time Receiver disabled 3 9 µs RECEIVER tr, tf Receiver output rise/fall time 12 30 ns tPHL, tPLH Receiver propagation delay time CL = 15 pF See Figure 6 75 100 ns tSK(P) Receiver pulse skew, |tPHL – tPLH| 3 15 ns tPLZ, tPHZ Receiver disable time 40 100 ns Driver enabled See Figure 7 20 50 ns tPZL(1), tPZH(1) Receiver enable time tPZL(2), tPZH(2) Driver disabled See Figure 8 3 8 µs SWITCHING CHARACTERISTICS 20 Mbps device (HVD75) bit time ≥ 50 ns (over recommended operating conditions) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER Driver differential output rise/fall 2 7 14 ns tr, tf time RL = 54 Ω, CL = 50 pF See Figure 3 tPHL, tPLH Driver propagation delay 7 11 17 ns tSK(P) Driver pulse skew, |tPHL – tPLH| 0 2 ns tPHZ, tPLZ Driver disable time 12 50 ns See Figure 4 and Receiver enabled 10 20 ns Figure 5 tPZH, tPZL Driver enable time Receiver disabled 3 7 µs RECEIVER tr, tf Receiver output rise/fall time 5 10 ns tPHL, tPLH Receiver propagation delay time CL = 15 pF See Figure 6 60 70 ns tSK(P) Receiver pulse skew, |tPHL – tPLH| 0 6 ns tPLZ, tPHZ Receiver disable time 15 30 ns Driver enabled See Figure 7 10 50 ns tpZL(1), tPZH(1) Receiver enable time tPZL(2), tPZH(2) Driver disabled See Figure 8 3 8 µs Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: SN65HVD72 SN65HVD75 SN65HVD78 |
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