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NCV7342D13R2G Datasheet(PDF) 11 Page - ON Semiconductor |
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NCV7342D13R2G Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 15 page NCV7342 http://onsemi.com 11 Table 6. CHARACTERISTICS VCC = 4.5 V to 5.5 V; VIO = 2.8V to 5.5 V (Note 8); TJ = −40 to +150°C; RLT = 60 W unless specified otherwise. On chip versions without VIO pin reference voltage for all digital inputs and outputs is VCC instead of VIO. Symbol Unit Max Typ Min Conditions Parameter VIO SUPPLY VOLTAGE (Pin VIO) Only for NCV7342−3 version VUVDVIO Undervoltage detection voltage on VIO pin 1.3 2.7 V THERMAL SHUTDOWN TJ(SD) Shutdown junction temperature junction temperature rising 160 180 200 °C TIMING CHARACTERISTICS (See Figure 7 and 8) td(TxD−BUSon) Delay TxD to bus active Ci = 100 pF between CANH to CANL 60 ns td(TxD−BUSoff) Delay TxD to bus inactive Ci = 100 pF between CANH to CANL 30 ns td(BUSon−RxD) Delay bus active to RxD CRxD = 15 pF 60 ns td(BUSoff−RxD) Delay bus inactive to RxD CRxD = 15 pF 70 ns tpd_dr Propagation delay TxD to RxD dominant to recessive transition Ci = 100 pF between CANH to CANL, CRxD = 15 pF 50 100 230 ns tpd_rd Propagation delay TxD to RxD recessive to dominant transition Ci = 100 pF between CANH to CANL, CRxD = 15 pF 50 120 230 ns td(stb−nm) Delay standby mode to normal mode 47 ms tWake Dominant time for wake−up via bus 0.5 5 ms tdwakerd Delay to flag wake event (recessive to dominant transitions) See Figure 5 Valid bus wake−up event, CRxD = 15 pF 1 10 ms tdwakedr Delay to flag end of wake event (dominant to recessive transition) See Figure 5 Valid bus wake−up event, CRxD = 15 pF 0.5 5 ms tdom(TxD) TxD dominant time for time out VTxD = 0 V 1.3 3 ms tdom(bus) Bus dominant time out Standby mode 1.3 3 ms 8. Only version NCV7342−3 has VIO supply pin. In NCV7342−0 this supply is provided from VCC pin. 9. Not tested in production. Guaranteed by design and prototype evaluation. 10.In case VIO > VCC, the limit is VIO + 0.3 V |
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