 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADSP-2185NKST-320 Datasheet(PDF) 15 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-2185NKST-320 Datasheet(HTML) 15 Page - Analog Devices |
|
|
15 / 48 page  ADSP-218xN Rev. A | Page 15 of 48 | August 2006 (BR) signal. If the ADSP-218xN is not performing an external memory access, it responds to the active BR input in the follow- ing processor cycle by: • Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, • Asserting the bus grant (BG) signal, and • Halting program execution. If Go Mode is enabled, the ADSP-218xN will not halt program execution until it encounters an instruction that requires an external memory access. If an ADSP-218xN series member is performing an external memory access when the external device asserts the BR signal, it will not three-state the memory interfaces nor assert the BG sig- nal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, re-enables the output drivers, and continues program execution from the point at which it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when an ADSP-218xN series member requires the external bus for a memory or BDMA access, but is stopped. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-218xN deasserts BG and BGH and executes the external memory access. FLAG I/O PINS ADSP-218xN series members have eight general-purpose pro- grammable input/output flag pins. They are controlled by two memory-mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-218xN’s clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. In addition to the programmable flags, ADSP-218xN series members have five fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0 to FL2 are dedicated output flags. FI and FO are available as an alternate configuration of SPORT1. Note: Pins PF0, PF1, PF2, and PF3 are also used for device con- figuration during reset. INSTRUCTION SET DESCRIPTION The ADSP-218xN series assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor’s unique architecture, offers the follow- ing benefits: • The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arith- metic add instruction, such as AR = AX0 + AY0, resembles a simple equation. • Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. • The syntax is a superset ADSP-2100 Family assembly lan- guage and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP-218xN’s interrupt vector and reset vector map. • Sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. • Multifunction instructions allow parallel execution of an arithmetic instruction, with up to two fetches or one write to processor memory space, during a single instruc- tion cycle. DEVELOPMENT SYSTEM Analog Devices’ wide range of software and hardware development tools supports the ADSP-218xN series. The DSP tools include an integrated development environment, an evalu- ation kit, and a serial port emulator. VisualDSP++ ®† is an integrated development environment, allowing for fast and easy development, debug, and deployment. The VisualDSP++ project management environment lets pro- grammers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder); a linker; a PROM-splitter utility; a cycle-accurate, instruction-level simu- lator; a C compiler; and a C run-time library that includes DSP and mathematical functions. Debugging both C and assembly programs with the VisualDSP++ debugger, programmers can: • View mixed C and assembly code (interleaved source and object information) • Insert break points • Set conditional breakpoints on registers, memory, and stacks • Trace instruction execution † VisualDSP++ is a registered trademark of Analog Devices, Inc. |
Similar Part No. - ADSP-2185NKST-320 |
|
Similar Description - ADSP-2185NKST-320 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
