NB3L853141

http://onsemi.com

2

6

Q1

Q2

Q3

Q4

17

18

16

15

14

13

12

4

35

7

8

9

11

10

Q4

Q3

Q2

Q1

Q0

19

20

2

1

Q0

EN

Power Supply to guarantee proper operation.

Figure 1. Pinout (Top View) and Logic Diagram

Table 1. FUNCTION TABLE

CLK0

CLK1

SEL

EN

Q

L

H

X

X

X

X

X

L

H

X

L

L

H

H

X

L

L

L

L

H

L

H

L

H

L*

*On next negative transition of CLK0 or CLK1

X = Don’t Care

Table 2. PIN DESCRIPTION

Pin Number

Name

I/O

Open

Default

Description

1

Q0

LVPECL Output

Non−Inverted Differential Clock Output

2

Q0

LVPECL Output

Inverted Differential Clock Output

3

Q1

LVPECL Output

Non−Inverted Differential Clock Output

4

Q1

LVPECL Output

Inverted Differential Clock Output

5

Q2

LVPECL Output

Non−Inverted Differential Clock Output

6

Q2

LVPECL Output

Inverted Differential Clock Output

7

Q3

LVPECL Output

Non−Inverted Differential Clock Output

8

Q3

LVPECL Output

Inverted Differential Clock Output

9

Q4

LVPECL Output

Non−Inverted Differential Clock Output

10

Q4

LVPECL Output

Inverted Differential Clock Output

11

VEE

Power

Negative Supply Voltage

12

SEL

LVCMOS / LVTTL

Input

Low

Clock Select Input. When HIGH, selects CLK1 input. When LOW,

selects CLK0, CLK0 inputs. Internal Pull−down Resistor.

13

NC

No Connect

14

CLK0

Multi−Level Input

High

Inverted Differential Clock Input. Internal Pull−up Resistor.

15

CLK0

Multi−Level Input

Low

Non−Inverted Differential Clock Input. Internal Pull−down Resistor.

16

CLK1

LVCMOS/LVTTL

Input

Low

Single−ended Clock Input. Internal Pull−down Resistor.

17

NC

No Connect

18

VCC

Power

Positive Supply Voltage

19

EN

LVCMOS/LVTTL

Input

Low

Synchronous Clock Enable Input. When Low, outputs are enabled.

When High, outputs are disabled Low. Internal Pull−down Resistor.

20

VCC

Power

Positive Supply Voltage

All VCC and VEE pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with

0.01 mF to GND.