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W25Q64FVSSIG Datasheet(PDF) 65 Page - Winbond |
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W25Q64FVSSIG Datasheet(HTML) 65 Page - Winbond |
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65 / 89 page  W25Q64FV Publication Release Date: October 07, 2013 - 65 - Revision L 6.2.38 Read Security Registers (48h) The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is automatically incremented to the next byte address after each byte of data is shifted out. Once the byte address reaches the last byte of the register (byte FFh), it will reset to 00h, the first byte of the register, and continue to increment. The instruction is completed by driving /CS high. The Read Security Register instruction sequence is shown in Figure 37. If a Read Security Register instruction is issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a maximum of FR (see AC Electrical Characteristics). ADDRESS A23-16 A15-12 A11-8 A7-0 Security Register #1 00h 0 0 0 1 0 0 0 0 Byte Address Security Register #2 00h 0 0 1 0 0 0 0 0 Byte Address Security Register #3 00h 0 0 1 1 0 0 0 0 Byte Address /CS CLK DI (IO 0) DO (IO 1) Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction (48h) High Impedance 8 9 10 28 29 30 31 24-Bit Address 23 22 21 3 2 1 0 Data Out 1 * /CS CLK DI (IO 0) DO (IO 1) 32 33 34 35 36 37 38 39 Dummy Byte High Impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 Data Out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = MSB * Figure 37. Read Security Registers Instruction (SPI Mode only) |
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