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TXP1XGGI2E00045G Datasheet(PDF) 5 Page - OPLINK Communications Inc. |
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TXP1XGGI2E00045G Datasheet(HTML) 5 Page - OPLINK Communications Inc. |
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5 / 9 page  Oplink Communications, Inc 5 S0120. Rev.03. 2011-05-11 TXP1XGGI2xx Application Notes Electrical Interface: All signal interfaces are compliant with the XFP MSA specification. The high speed DATA interface is differential AC-coupled internally and can be directly connected to a 3.3V SERDES IC. RX_LOS: The Loss of Signal circuit monitors the level of the incoming optical signal and generates a logic HIGH when an insufficient photocurrent is produced. TX_Dis: When the TX Disable pin is at logic HIGH, the transmitter optical output is disabled. (less than -45dBm). P_Down: The Power Down Function pin, when held High by the host, places the module in the standby (Low Power) mode with a maximum power dissipation of 1.5W. This protects hosts which are not capable of cooling higher power modules which may be accidentally inserted.The module’s 2-wire serial interface and all laser safety functions must be fully functional in this low power mode. During P_Down, the module shall still support the completion of reset Interrupt, as well as maintain functionality of the variable power supply. Mod_NR: The Mod_NR is an output pin that when High, indicates that the module has detected a condition that renders transmitter and or receiver data invalid, shall consist of logical OR of the following signals: • Transmit Signal Conditioner Loss of Lock • Transmitter Laser Fault • Receiver Signal Conditioner Loss of Lock Other conditions deemed valuable to the detection of fault may be added to the Mod_NR. The Mod_NR output pin is an open collector and must be pulled to Host_Vcc on the host board. P_Down/RST: The negative edge of Reset Function signal initiates a complete module reset. Module Behavior During P_Down and RST: During execution of a reset (t_init) or while held in Power Down mode, a module may be unable to determine the correct value for Mod_NR and RX_LOS. These outputs as well as all interrupt related flags, except completion of Reset flag, shall be disregarded by the host. When the module completes a Reset and is not in Power Down mode, the module must represent the correct value of both signals on its outputs before posting a completion of reset interrupt to the host. At no time shall a module cause spurious assertion of the Interrupt pin.When a host initially applies power to a module with the P_Down/RST signal asserted, a module comes up in power down mode.The module shall only assert the Interrupt signal pin to inform the host it has completed a reset. The completion of reset flag shall be the only interrupt source flag set during power down mode. The host is expected to clear this interrupt before releasing the module from the power down mode. The transition from power down mode to normal mode will trigger a reset of the module and result in a 2nd module reset and a 2nd reset completion interrupt to the host. PowerSupplyandGrounding:The power supply line should be well-filtered. All 0.1μF power supply bypass capacitors should be as close to the transceiver module as possible. Host Board Termination & Coupling All caps are in units of µF TD- TD+ RD+ RD- ASIC/ SerDes CML INPUTS CML OUTPUTS + 0.1 10 +1.8V +3.3V +3.3V +3.3V SCL, SDA, Mod_Abs, Mod_NR, R R R XFP Interrupt, RX_LOS 20, 22 6 + +5.0V + +3.3V 8, 9 1µH coil or ferrite inductor 1µH coil or ferrite inductor 1µH coil or ferrite inductor 0.1 0.1100.1 0.1100.1 |
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Similar Description - TXP1XGGI2E00045G |
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