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AM29LV160DT-70EI Datasheet(PDF) 4 Page - Advanced Micro Devices

Part No. AM29LV160DT-70EI
Description  16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29LV160DT-70EI Datasheet(HTML) 4 Page - Advanced Micro Devices

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Am29LV160D
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TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29LV160D Device Bus Operations ................................9
Word/Byte Configuration .......................................................... 9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences ............................ 10
Program and Erase Operation Status .................................... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Sector Address Tables (Am29LV160DT) ..........................12
Table 3. Sector Address Tables (Am29LV160DB) ..........................13
Autoselect Mode ..................................................................... 14
Table 4. Am29LV160D Autoselect Codes (High Voltage Method) ..14
Sector Protection/Unprotection ............................................... 14
Temporary Sector Unprotect .................................................. 15
Figure 1. Temporary Sector Unprotect Operation........................... 15
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 16
Common Flash Memory Interface (CFI) . . . . . . . 17
Table 5. CFI Query Identification String ..........................................17
Table 6. System Interface String .....................................................18
Table 7. Device Geometry Definition ..............................................18
Hardware Data Protection ...................................................... 19
Table 8. Primary Vendor-Specific Extended Query ........................19
Low VCC Write Inhibit .............................................................. 19
Write Pulse “Glitch” Protection ............................................... 19
Logical Inhibit .......................................................................... 19
Power-Up Write Inhibit ............................................................ 19
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20
Reading Array Data ................................................................ 20
Reset Command ..................................................................... 20
Autoselect Command Sequence ............................................ 20
Word/Byte Program Command Sequence ............................. 20
Unlock Bypass Command Sequence ..................................... 21
Figure 3. Program Operation .......................................................... 21
Chip Erase Command Sequence ........................................... 21
Sector Erase Command Sequence ........................................ 22
Erase Suspend/Erase Resume Commands ........................... 22
Figure 4. Erase Operation............................................................... 23
Command Definitions ............................................................. 24
Table 9. Am29LV160D Command Definitions ................................24
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 25
DQ7: Data# Polling ................................................................. 25
Figure 5. Data# Polling Algorithm ................................................... 25
RY/BY#: Ready/Busy# ........................................................... 26
DQ6: Toggle Bit I .................................................................... 26
DQ2: Toggle Bit II ................................................................... 26
Reading Toggle Bits DQ6/DQ2 ............................................... 26
Figure 6. Toggle Bit Algorithm........................................................ 27
DQ3: Sector Erase Timer ....................................................... 28
Table 10. Write Operation Status ................................................... 28
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29
Figure 7. Maximum Negative Overshoot Waveform ...................... 29
Figure 8. Maximum Positive Overshoot Waveform........................ 29
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 29
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 31
Figure 10. Typical ICC1 vs. Frequency ........................................... 31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. Test Setup..................................................................... 32
Table 11. Test Specifications ......................................................... 32
Figure 12. Input Waveforms and Measurement Levels ................. 32
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Read Operations .................................................................... 33
Figure 13. Read Operations Timings ............................................. 33
Hardware Reset (RESET#) .................................................... 34
Figure 14. RESET# Timings .......................................................... 34
Word/Byte Configuration (BYTE#) ........................................ 35
Figure 15. BYTE# Timings for Read Operations............................ 35
Figure 16. BYTE# Timings for Write Operations............................ 35
Erase/Program Operations ..................................................... 36
Figure 17. Program Operation Timings.......................................... 37
Figure 18. Chip/Sector Erase Operation Timings .......................... 38
Figure 19. Data# Polling Timings (During Embedded Algorithms). 39
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 39
Figure 21. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations ............................................................ 40
Figure 22. Temporary Sector Unprotect/Timing Diagram .............. 40
Figure 23. Sector Protect/Unprotect Timing Diagram .................... 41
Figure 24. Alternate CE# Controlled Write Operation Timings ...... 43
Erase and Programming Performance . . . . . . . 44
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 44
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 44
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 45
TS 048—48-Pin Standard TSOP ............................................ 45
TSR048—48-Pin Reverse TSOP ........................................... 46
FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
8 x 9 mm ................................................................................ 47
SO 044—44-Pin Small Outline Package ................................ 48
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision A (January 1999) ..................................................... 49
Revision A+1 (April 19, 1999) ................................................. 49
Revision B (November 23, 1999) ............................................ 49
Revision B+1 (February 22, 2000) .......................................... 49
Revision B+2 (November 7, 2000) ......................................... 49
Revision B+3 (November 10, 2000) ....................................... 49


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