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XR88C681J-F Datasheet(PDF) 7 Page - Exar Corporation |
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XR88C681J-F Datasheet(HTML) 7 Page - Exar Corporation |
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7 / 101 page  XR88C681 7 Rev. 2.11 44 PLCC 40 PDIP, CDIP 28 PDIP Symbol Type Description 38 34 25 RESET I Master Reset (Active High). Asserting this input clears in- ternal registers, SR, ISR, IMR, OPR, OPCR, and initializes the IVR to 0F16. Asserting this input also stops the Counter/ Timer, puts OP0 - OP7 in the high state, and places both serial channels in the inactive state with TXDA and TXDB outputs marking (high). 39 35 26 -CS I Chip Select (Active Low). The data bus is tri-stated when -CS is “high.” Data transfers between the CPU and the DUART via D0 - D7 are enabled when -CS is “low”. 40 36 27 IP2 (C/T_EX) I Input 2. (General Purpose Input). This input pin can also be programmed to function as the “Counter/Timer external clock” input (C/T_EX). 41 37 IP6 (RXCB) I Input 6 (I-Mode). General Purpose Input pin. This input pin can also be programmed to function as the External Receiv- er Clock for Channel B (RXCB). 41 37 -IACK I Interrupt Acknowledge Input (Z-Mode). Active Low. This input is the CPU’s response to the Interrupt Request issued by the DUART device. When the CPU asserts this input, it indicates that the DUART’s interrupt request is about to be serviced, and that the very next cycle will be an Inter- rupt Acknowledge Cycle. The DUART will respond to the CPU’s Interrupt Acknowledge by placing the contents of the Interrupt Vector Register (IVR) on the data bus (D0 - D7). 42 38 IP5 (TXCB) I Input 5 (I-Mode). General Purpose Input pin. This pin can also be configured to function as the external clock input for the Transmitter of Channel B (TXCB). 42 38 IEO (Z-Mode) O Interrupt Enable Output (Z-Mode). Active High. This output pin is normally “high”. However, either of the following two conditions can cause this output pin to be ne- gated (toggled “low”). 1. If the IEI (Interrupt Enable Input) pin is “low”. If IEO is “low” because of the IEI pin, IEO will toggle “high” once the IEI has toggled “high”. 2. The DUART has issued an Interrupt Request to the CPU (-INTR pin is toggled “low”). If IEO is “low” because the DUART has requested an Interrupt, then IEO will remain “low”, throughout the Interrupt Service Routine, until the CPU has invoked the “” command. 43 39 IP4 (RXCA) I Input 4 (I-Mode). General Purpose Input pin. This input pin can also be configured to function as the external clock input for the Receiver of Channel A (RXCA). 43 39 IEI (Z-Mode) I Interrupt Enable Input (Z-Mode). Active High. If this active-high input is at a logic “high”, the DUART is ca- pable of generating all non-masked Interrupt Requests to the CPU. If this input is at a logic “low”, the DUART is inhibited from generating any Interrupt Requests to the CPU. 44 40 28 VCC PWR Most Positive Power Supply. |
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