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AM29LV008BT-70REI Datasheet(PDF) 7 Page - Advanced Micro Devices

Part No. AM29LV008BT-70REI
Description  8 Megabit (1 M x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
Download  38 Pages
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
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AM29LV008BT-70REI Datasheet(HTML) 7 Page - Advanced Micro Devices

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Am29LV008B
7
P R E L I M I NARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29LV008B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A19–A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing waveforms. ICC1 in
the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The Am29LV008B is manufactured on AMD’s new 0.35
µm process technology and offers an Unlock Bypass
mode to facilitate faster programming. Once the device
enters the Unlock Bypass mode, only two write cycles
are required to program a byte, instead of four. Devices
manufactured on AMD’s 0.5
µm process technology re-
quire a four-bus-cycle command sequence for each byte
programmed. The “Byte Program Command Sequence”
section has details on programming data to the device
using both standard and Unlock Bypass command se-
quences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
uniquely select a sector. The “Command Definitions”
Operation
CE#
OE#
WE#
RESET#
Addresses (Note 1)
DQ0–DQ7
Read
L
L
H
H
AIN
DOUT
Write
L
H
L
H
AIN
DIN
Standby
VCC ±
0.3 V
XX
VCC ±
0.3 V
X
High-Z
Output Disable
L
H
H
H
X
High-Z
Reset
X
X
X
L
X
High-Z
Sector Protect (Note 2)
L
H
L
VID
Sector Address, A6 = L,
A1 = H, A0 = L
DIN, DOUT
Sector Unprotect (Note 2)
L
H
L
VID
Sector Address, A6 = H,
A1 = H, A0 = L
DIN, DOUT
Temporary Sector Unprotect
X
X
X
VID
AIN
DIN


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