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AM29BDS323D Datasheet(PDF) 20 Page - Advanced Micro Devices |
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AM29BDS323D Datasheet(HTML) 20 Page - Advanced Micro Devices |
20 / 44 page 20 Am29BDS323D P R E L I M INARY Command Definitions Table 4. Command Definitions Legend: X = Don’t care RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A20–A12 uniquely select any sector. BA = Address of the bank (A20, A19) that is being switched to autoselect mode, is in bypass mode, or is being erased. SLA = Address of the sector to be locked. Set sector address (SA) and either A6 = 1 for unlocked or A6 = 0 for locked. WS = Number of wait states defined by A12, A13. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD and PD. 5. Unless otherwise noted, address bits A20–A11 are don’t cares. 6. No unlock or command cycles required when bank is reading array data. 7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information). 8. The fourth cycle of the autoselect command sequence is a read cycle. The system must provide the bank address. See the Autoselect Command Sequence section for more information. 9. The fifth cycle of the device ID autoselect command sequence is an extended device ID code. The data is 00h for devices that do not require additional latency when burst address begins at an address boundary, and 20h for devices that require additional latency when burst address begins at an address boundary. 10. The data is 0000h for an unlocked sector and 0001h for a locked sector. All sectors are again locked upon hardware reset. 11. The Unlock Bypass command is required prior to this command sequence. 12. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 13. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. The Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. The addresses in the third cycle must contain, on A12 and A13, the additional wait counts to be set. See “Set Wait State Command Sequence”. Command Sequence (Note 1) Bus Cycles (Notes 2–5) First Second Third Fourth Fifth Sixth Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Asynchronous Read (Note 6) 1 RA RD Reset (Note 7) 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 (BA)555 90 (BA)X00 0001 Device ID (Note 9) 4 555 AA 2AA 55 (BA)555 90 (BA)X01 22D1 (BA)X03 20/00 Sector Lock Verify (Note 10) 4 555 AA 2AA 55 (SA)555 90 (SA)X02 00/01 Program 4 555 AA 2AA 55 555 A0 PA Data Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program (Note 11) 2 XXX A0 PA PD Unlock Bypass Sector Erase (Note 11) 2 XXX 80 SA 30 Unlock Bypass Chip Erase (Note 11) 2 XXX 80 XXX 10 Unlock Bypass Reset (Note 12) 2 BA 90 XXX 00 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase Suspend (Note 13) 1 BA B0 Erase Resume (Note 14) 1 BA 30 Sector Lock/Unlock 3 XXX 60 XXX 60 SLA 60 Set Wait Count (Note 15) 3 555 AA 2AA 55 (WS)555 C0 Enable PS Mode 3 555 AA 2AA 55 555 70 |
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