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AD976ACN Datasheet(PDF) 10 Page - Analog Devices |
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AD976ACN Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page AD976/AD976A –10– REV. C OFFSET AND GAIN ADJUSTMENT The AD976/AD976A is factory trimmed to minimize gain, offset and linearity errors. In some applications, where the ana- log input signal is required to meet the full dynamic range of the ADC, the gain and offset errors need to be externally trimmed to zero. Figure 7 shows the required trim circuitry to correct for these offset and gain errors. Figure 8 shows the bipolar transfer characteristic of the AD976/AD976A. Where adjustment is required, offset error must be corrected before gain error. To achieve this, trim the offset resistor R3 while the input voltage is 1/2 LSB below ground. By applying a voltage of –152.6 µV at the input and adjusting the potentiom- eter until the major carry transition is located between 1111 1111 1111 1111 and 0000 0000 0000 0000, the internal offset can be corrected. To adjust the gain error, an analog signal should be input at either the first code transition (ADC negative full-scale) or the last code transition (ADC positive full-scale). Thus, to adjust for full-scale error, an input voltage of 9.999542 V (FS/2–3/2 LSBs) can be applied to the input and R4 should be adjusted until the output code flickers between the last positive code transition 0111 1111 1111 1111 and 0111 1111 1111 1110. Should the first code transition need adjusting, the trim procedure should consist of applying an analog input signal of –9.999847 V (–FS/2 + 1/2 LSB) to the input and adjusting the trim until the output code flickers between 1000 0000 0000 0000 and 1000 0000 0000 0001. The external 200 Ω and 33.2K resistor shown in the data sheet for the AD976 provide compensation for an internal adjustment of the offset and gain which allows calibration with a single supply. These resistors may not be required in some applications but it should be noted that their removal will result in offset and gain errors in addition to those listed in the electrical specifications of the data sheet. Tables I and II illustrate the worst case range for Bipolar Zero (offset) error and Full-Scale (gain) error for the AD976 and the AD976A. All error terms are with respect to the A/D (i.e., a negative offset in the table would have to be corrected with an externally applied positive voltage). R5 576k +5V R4 50k VIN AGND1 REF CAP AGND2 10V INPUT R2 33.2k C2 2.2 F AD976/ AD976A R1 200 C1 2.2 F R3 50k Figure 7. Input Connection with Offset and Gain Adjustment OUTPUT CODE 011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 0V (VREF/2) – 1 LSB (VREF/2) + 1 LSB + FS – 1 LSB FS = VREFV 1LSB = FS 65536 VREF/2 VIN = (AIN(+) - AIN(-)) – INPUT VOLTAGE Figure 8. The Bipolar Transfer Characteristic of the AD976/AD976A Table I. Offset and Gain Error for AD976 With Both External Without the External With the External 33.2K Without Either External Error Term Resistors Included 33.2K Resistor Resistor Grounded Resistors Included Offset Error –10 mV < Error < 10 mV –25 mV < Error < –5 mV –25 mV < Error < –5 mV –40 mV < Error < –15 mV +Full Scale –0.50% < Error < 0.50% 1 –0.05% < Error < 0.95% –0.65% < Error < 0.35% 0.55% < Error < 1.90% Error –0.25% < Error < 0.25%2 –Full Scale –0.50% < Error < 0.50%1 0.25% < Error < 1.25% –0.65% < Error < 0.35% –2.5% < Error < –1.0% Error –0.25% < Error < 0.25% 2 Table II. Offset and Gain Error for AD976A With Both External Without the External With the External 33.2K Without Either External Error Term Resistors Included 33.2K Resistor Resistor Grounded Resistors Included Offset Error –10 mV < Error < 10 mV –25 mV < Error < –5 mV –25 mV < Error < –5 mV –55 mV < Error < –25 mV +Full Scale –0.50% < Error < 0.50% 1 –0.05% < Error < 0.95% –0.65% < Error < 0.35% 1.0% < Error < 2.50% Error –0.25% < Error < 0.25% 2 –Full Scale –0.50% < Error < 0.50% 1 0.25% < Error < 1.25% –0.65% < Error < 0.35% –3.50% < Error < –1.75% Error –0.25% < Error < 0.25% 2 NOTES 1For A grade part. 2For B grade part. |
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