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LPC2106FBD48 Datasheet(PDF) 8 Page - NXP Semiconductors |
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LPC2106FBD48 Datasheet(HTML) 8 Page - NXP Semiconductors |
8 / 41 page LPC2104_2105_2106_7 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 07 — 20 June 2008 8 of 41 NXP Semiconductors LPC2104/2105/2106 Single-chip 32-bit microcontrollers P0.11/CTS1/CAP1.1 36[1] I/O P0.11 — Port 0 bit 11. I CTS1 — Clear to Send input for UART 1. I CAP1.1 — Capture input for Timer 1, channel 1. P0.12/DSR1/MAT1.0 37[1] I/O P0.12 — Port 0 bit 12. I DSR1 — Data Set Ready input for UART 1. O MAT1.0 — Match output for Timer 1, channel 0. P0.13/DTR1/MAT1.1 41[1] I/O P0.13 — Port 0 bit 13. O DTR1 — Data Terminal Ready output for UART 1. O MAT1.1 — Match output for Timer 1, channel 1. P0.14/DCD1/EINT1 44[1] I/O P0.14 — Port 0 bit 14. I DCD1 — Data Carrier Detect input for UART 1. I EINT1 — External interrupt 1 input. P0.15/RI1/EINT2 45[1] I/O P0.15 — Port 0 bit 15. I RI1 — Ring Indicator input for UART 1. O EINT2 — External interrupt 2 input. P0.16/EINT0/MAT0.2 46[1] I/O P0.16 — Port 0 bit 16. I EINT0 — External interrupt 0 input. O MAT0.2 — Match output for Timer 0, channel 2. P0.17/CAP1.2/TRST 47[1] I/O P0.17 — Port 0 bit 17. I CAP1.2 — Capture input for Timer 1, channel 2. I TRST — Test Reset for JTAG interface, primary JTAG pin group. P0.18/CAP1.3/TMS 48[1] I/O P0.18 — Port 0 bit 18. I CAP1.3 — Capture input for Timer 1, channel 3. I TMS — Test Mode Select for JTAG interface, primary JTAG pin group. P0.19/MAT1.2/TCK 1[1] I/O P0.19 — Port 0 bit 19. O MAT1.2 — Match output for Timer 1, channel 2. I TCK — Test Clock for JTAG interface, primary JTAG pin group. P0.20/MAT1.3/TDI 2[1] I/O P0.20 — Port 0 bit 20. O MAT1.3 — Match output for Timer 1, channel 3. I TDI — Test Data In for JTAG interface, primary JTAG pin group. P0.21/PWM5/TDO 3[1] I/O P0.21 — Port 0 bit 21. O PWM5 — Pulse Width Modulator output 5. O TDO — Test Data Out for JTAG interface, primary JTAG pin group. P0.22/TRACECLK 32[4] I/O P0.22 — Port 0 bit 22. O TRACECLK — Trace Clock. Standard I/O port with internal pull-up. P0.23/PIPESTAT0 33[4] I/O P0.23 — Port 0 bit 23. O PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up. P0.24/PIPESTAT1 34[4] I/O P0.24 — Port 0 bit 24. O PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up. P0.25/PIPESTAT2 38[4] I/O P0.25 — Port 0 bit 25. O PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up. Table 3. Pin description …continued Symbol Pin Type Description |
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