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MP28248 Datasheet(PDF) 15 Page  Monolithic Power Systems 

MP28248 Datasheet(HTML) 15 Page  Monolithic Power Systems 
15 / 19 page MP28248 ? 3A, 4.2V20V INPUT, FASTTRANSIENT SYNCHRONOUS STEPDOWN CONVERTER IN QFN12 (2X3mm) MP28248 Rev 1.0 www.MonolithicPower.com 15 1/5/2012 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2012 MPS. All Rights Reserved. APPLICATION INFORMATION Setting the Output Voltage?Large ESR Capacitors For applications that use electrolytic or POS capacitors as output capacitors, the output voltage is set by feedback resistors R1 and R2 as shown in Figure 10. Figure 10: Simplified Circuit of POS Capacitor To design the feedback circuit, first select a value for R2: a small R2 will lead to considerable quiescent current loss while a large R2 makes the FB pin noisesensitive. For best results, choose a value between 5k? and 50k? for R2, and choose a comparatively larger R2 when VO is low?e.g. 1.05V?and a smaller R2 when VO is high. Then determine R1 using the following equation that takes the output ripple into consideration: OUT OUT REF 12 REF 1 VV V 2 RR V ?? ? ?? (12) Where OUT V ? is the output ripple determined by equation 21. Setting the Output Voltage?Small ESR Capacitors Figure 11: Simplified Circuit with Ceramic Capacitor When using a lowESR ceramic capacitors on the output, add an external voltage ramp to the FB pin. As Figure 11 shows, the resistive divider and the ramp voltage, VRAMP, influences the output voltage. As discussed in the previous section, the VRAMP can be calculated as per equation 7. Select an appropriate R2: typically in the range of 5k? to 50k? for most applications; use a relatively large R2 when VO is low? e.g.,1.05V?and a small R2 when VO is high. Determine R1 as follows: 2 1 FB(AVG) 2 OUT FB(AVG) 4 9 R R= V R  (V V ) R +R (13) Where VFB(AVG) is the average value on the FB pin. Its value in skip mode is lower than in PWM mode, meaning load regulation is strictly conditional to to the VFB(AVG). Line regulation is also related to VFB(AVG). For improved load or line regulation, use a lower VRAMP as per equation 9. For PWM mode, use the following equation to determine VFB(AVG): 12 FB(AVG) REF RAMP 12 9 R//R 1 VV V 2R //R R ?? ? ? (14) Typically R9 is 0?, but the appropriate nonzero value, as per equation 15, improves noise immunity. Select a value that is around 0.2×R1//R2 to minimize its effect on VRAMP. ? ?? ? 9 4SW 1 R 2C 2f (15) To simplify the calculation of R1 for equation 14, add a DCblocking capacitor, CDC, to filter the DC influence from R4 and R9. Figure 12 shows a simplified circuit with external ramp compensation and a DCblocking capacitor. Approximating R1 is now much easier with CDC using equation 16 for PWM mode. ?? ? ? OUT REF RAMP 12 REF RAMP 1 (V V V ) 2 RR 1 VV 2 (16) Select a CDC value at least 10× the value of C4 for better DC blocking, though do not select a CDC that exceeds 0.47µF to avoid long startup times. Larger CDC values improve FB noise immunity when combined with smaller R1 and R2 values to limit system startup effects. Note that even with CDC, the load and line regulation are still VRAMPrelated. 
