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MP28248 Datasheet(PDF) 13 Page - Monolithic Power Systems

Part No. MP28248
Description  High-Efficiency, Fast-Transient, 3A, 4.2V-20V Input Synchronous Step-down Converter in a QFN12 (2x3mm) Package
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Maker  MPS [Monolithic Power Systems]
Homepage  http://www.monolithicpower.com
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MP28248 Datasheet(HTML) 13 Page - Monolithic Power Systems

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MP28248 – 3A, 3.3V-20V INPUT, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER IN 2X3MM QFN
MP28248 Rev. 1.0
www.MonolithicPower.com
13
1/5/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
Ramp with small ESR Capacitor
When using ceramic output capacitors, the ESR
is insufficient to stabilize the system and requires
external ramp compensation. The application
section discusses this in further depth.
.
Figure 8: Simplified Circuit in PWM Mode with
External Ramp Compensation
Figure 8 shows a simplified external ramp
compensation circuit (R4 and C4) for PWM mode,
with the HS-FET off. Chose R1, R2, and C4 of
the external ramp to meet the following condition:
12
9
SW
4
1
2
RR
11
<+R
2π fC
5
R +R




(5)
Where:
R4
C4
FB
C4
II
I
I

(6)
And VRAMP on VFB can then be estimated as:


IN
OUT
12
RAMP
ON
44
1
2
9
VV
R//R
Vt
RC
R //R
R
(7)
The downward slope of the VFB ripple then
follows:

OUT
RAMP
SLOPE1
off
4
4
V
V
V
tR
C
(8)
As shown in equation 8, either reduce R4 or C4 if
there is instability in PWM mode. If C4 can not be
reduced further due to limitation from equation 5,
then reduce R4. For stable PWM operation,
design Vslope1 based on equation 9.

SW
ON
ESR
OUT
slope1
OUT
OUT
SW
on
tt
+-R
C
Io(mA)
0.7 π
2
-V
V
+
2L C
t
-t
(9)
Where IO is the load current.
In skip mode, the downward slope of the VFB
ripple is the same whether the external ramp is
used or not. Figure 9 shows the simplified circuit
of the skip mode when both the HS-FET and LS-
FET are off.
Figure 9: Simplified Circuit in Skip Mode
The downward slope of the VFB ripple in skip
mode can be determined as follow:

REF
SLOPE2
12
OUT
V
V
(R
R // Ro) C

(10)
Where RO is the equivalent load resistor.
As shown in Figure 6, VSLOPE2 in skip mode is
lower than that is in the PWM mode, so generally
the jitter in skip mode is larger. For a system with
less jitter in light-load condition, select smaller
VFB resistors, though smaller resistors decrease
the light-load efficiency.
When using a large-ESR capacitor on the output,
add a 10µF or smaller ceramic capacitor in
parallel to minimize ESL effects.
Soft-Start/Stop
The MP28248 employs a soft start/stop (SS)
mechanism to ensure smooth output during
power up and power shut-down. When the EN
pin goes high, an internal current source (14μA)
charges up the external SS cap. The SS cap
voltage takes over the REF voltage to the PWM
comparator. The output voltage smoothly ramps
up with the SS voltage. Once the SS voltage
reaches VREF, it continues to ramp up while the
PWM comparator only compares the VREF and
the VFB. At this point, the soft start finishes and it
enters into steady state operation.
When the EN pin goes low, an internal 4.5μA
current source discharges the external SS cap
voltage. Once the SS voltage falls below the
VREF, the PWM comparator will only compare the
VFB to the SS voltage. The output voltage will
decrease smoothly with the SS voltage until the
voltage level zeros out at high load. The SS cap
value can be determined as follows:


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